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IEEE VLSI PROJECTS

Projectsatbangalore, offers VLSI Projects to students in various areas like

IEEE 2016 VLSI PROJECTS

1. VLSI Implementation of an adaptive Edge Enhanced color interpolation Processor for Real-Time Video Applications

2. Demonstrating HW-SW Transient Error Mitigation on the single-chip cloud computer data plane

3. Enhanced Memory reliability against multiple cell upsets using Decimal Matrix code

4. Wear out Resilience in NOCs through an Aging Aware Adaptive Routing Algorithm

5. High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications On-Chip Memory Hierarchy in one Coarse-Grained Reconfigurable Architecture to compress memory space and to reduce time

6. A Voltage based Leakage current calculation scheme and its application to Nanoscale and FinFET Standard cell designs

7. High Throughput and Low complexity BCH decoding Architecture for Solid-State Drives

8. Nonbinary LDPC Decoder based on Simplified Enhanced Generalized Bit-Flipping Algorithm

9. A 2-D Interpolation based ORD Processor with Partial Layer Mapping for MIMO-OFDM Systems

10.Digitally controlled Pulse Width Modulator for On-Chip Power Management

11. UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors

12. High-Throughput Multistandard Transform Core supporting MPEG/H.264/VC-1 using Common Shared Distributed Arithmetic

13. Alogirthm and Architecture for a Low-Power Content Addressable Memory based on Sparse Clustered Networks

14. A Variation-Aware Preferential Design approach for Memory- Based Reconfigurable Computing

15. Asynchronous Domino Logic Pipeline Design Based on Constructed Critical data path

16. Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes

17. Application Mapping Onto Mesh-Based Network-On-Chip using Discrete Particle Swarm Optimization

18. Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications

19. Single-Bit Pseudo Parallel Processing Low-oversampling Delta-Sigma Modulator suitable for SDR Wireless Transmitters

20. A Lattice Reduction Aided MIMO Channel Equalizer in 90 nm CMOS achieving 720 Mb/s

21. Low Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS Amplifiers

22. Low-Energy Two-stage Algorithm for High Efficiency Epileptic Seizure Detection

23. An Ultralow Power Multirate FSK Demodulator for High-Speed Biomedical Zero-IF Receivers

24. Ultra-High Throughput Low-Power Packet Classification

25. Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SOC's

26. Area-Delay-Power Efficient Fixed-point LMS Adaptive filter with low adaptation delay

27. Energy Efficiency Optimization through codesign of the Transmitter and Receiver in High-speed On-Chip Interconnects

28. A Fast application based supply voltage optimization method for dual voltage FPGA

29. Reliable Low-Power Multiplier Design using Fixed-Width Replica Redundancy block

30. Low-Power Pulse-Triggered Flip-Flop Design based on a signal feed-through




2017 IEEE VLSI Projects



1. A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter For Sub-mW Energy Harvesting Applications

2. A Generalization Of Addition Chains And Fast Inversions In Binary Fields

3. A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of Dct

4. A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic

5. A Multicycle Test Set Based On A Two-Cycle Test Set With Constant Primary Input Vectors

6. A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems

7. A Synergetic Use Of Bloom Filters For Error Detection And Correction

8. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

9. Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks

10. An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm For Reconfigurable Fir Filter Synthesis

11. Comments On "Low-Latency Digit-Serial Systolic Double Basis Multiplier Over GF (2m ) Using Subquadrat Ic Toeplitz Matrix- Vector Product Approach"

12. Communication Optimization Of Iterative Sparse Matrix - Vector Multiply On GPUs And FPGAs

13. Efficient Coding Schemes For Fault-Tolerant Parallel Filters

14. Efficient Sub Quadratic Space Complexity Architectures For Parallel Mpb Single- And 16. For All Trinomials Using Toeplitz Matrix-Vector Product Decomposition

15. Fast Sign Detection Algorithm For The Rns Moduli Set {2n+1 - 1, 2n - 1,2n}

16. Fault Tolerant Parallel Filters Based On Error Correction Codes

17. Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications

18. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

19. Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For DSRC Applications

20. High - Throughput Finite Field Multipliers Using Redundant Basis For Fpga And Asic Implementations

21. Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes

22. Low-Complexity Tree Architecture For Finding The First Two Minima

23. Low-Latency High-Throughput Systolic Multipliers Over For Nist Recommended Pentanomials

24. Low-Power And Area-Efficient Shift Register Using Pulsed Latches

25. Low-Power Programmable PRPG With Test Compression Capabilities

26. Mixing Drivers In Clock-Tree For Power Supply Noise Reduction

27. New Regular Radix-8 Scheme For Elliptic Curve Scalar Multiplication Without Pre-Computation

28. Novel Block-Formulation And Area-Delay - Efficient Reconfigurable Interpolation Filter Architecture Formulti - Standard SDR Applications

29. Novel Shared Multiplier Scheduling Scheme For Area-Efficient FFT/IFFT Processors

30. Obfuscating DSP Circuits Via High-Level Transformations

31. One Minimum Only Trellis Decoder For Non – Binary Low - Density Parity - Check Codes

32. Partially Parallel Encoder Architecture For Long Polar Codes

33. Piecewise-Functional Broadside Tests Based On Reachable States

34. Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding

35. Recursive Approach To The Design Of A Parallel Self-Timed Adder

36. Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block

37. Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures

38. Simplified Trellis Min–Max Decoder Architecture For Nonbinary Low-Density Parity-Check Codes

39. Skewed-Load Test Cubes Based On Functional Broadside Tests For A Low-Power Test Set

40. VLSI Computational Architectures For The Arithmetic Cosine Transform

41. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
42. Graph-Based Transistor Network Generation Method for Supergate Design

43. High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design

44. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

45. High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule

46. Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

47. In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

48. Integrating Lock-Free and Combining Techniques for a Practical and Scalable FIFO Queue

49. Learning Weighted Lower Linear Envelope Potentials in Binary Markov Random Fields

50. Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs

51. Long-Distance Measurement Applying Two High-Stability and Synchronous Wavelengths

52. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

53. MAC With Action-Dependent State Information at One Encoder

54. Minimum Parallel Binary Adders with NOR (NAND) Gates

55. Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder

56. Modulation Classification of Single-Input Multiple-Output Signals Using Asynchronous Sensors

57. Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications

58. Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System FIR Filter

59. Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications

60. Obfuscating DSP Circuits via High-Level Transformations

61. One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes

62. Partially Parallel Encoder Architecture for Long Polar Codes

63. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding

64. Range Unlimited Delay-Interleaving and –Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit

65. Recursive Approach to the Design of a Parallel Self-Timed Adder

66. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
67. Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI

68. Shift Register Design Using Two Bit Flip-Flop

69. Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent Reception

70. Synthesis of Genetic Clock with Combinational Biologic Circuits

71. Timing Error Tolerance in Small Core Designs for SoC Applications

72. Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters FIR Filter

73. VLSI-Assisted Non-rigid Registration Using Modified Demons Algorithm

For VLSI FPGA IEEE 2016-2017 Project Titles Email to: [email protected]



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