VLSI Projects 2022
2023-2024 VLSI Mini Projects using VHDL
History of VHDL:
In 1980, the USA Department of Defence wanted to make circuit design self documenting, follow a common design methodology and be reusable with new technologies. The DoD funded a project under the Very High Speed Integrated Circuit (VHSIC) program to create a standard hardware description language. In 1983, The DoD established requirements for a standard VHSIC Hardware Description Language (VHDL). A group of IBM, TI and Intermetrics Corporations worked together to develop the VHDL. VHDL 2.0 was released only 6 months after the project began. VHDL 6.0 was released in December of 1984. Development of VHDL-based tools also began in 1984. In 1985, ITAR restrictions were lifted from VHDL and its related software, and the VHDL 7.2 Language Reference Manual (LRM) copyright was referred to IEEE for further development and standardisation. This led to the development of the IEEE 1073A VHDL LRM. Later that year version B of LRM was developed and approved by a committee of the IEEE Standard Board (VHDL 1076-1987).
2023-2024 VLSI Mini Projects using Xilinx
How to Design in Xilinx:
Xilinx's line of products expanded to a broad range of FPGAs, complex programmable logic devices (CPLDs), design tools, intellectual property and reference designs.Xilinx also has a global services and training program.In 2011, Xilinx introduced the Virtex-7 2000T, the first product based on 2.5D stacked silicon (based on silicon interposer technology) to deliver larger FPGAs than could be built using standard monolithic silicon. Xilinx then adapted the technology to combine formerly separate components in a single chip, first combining an FPGA with transceivers based on heterogeneous process technology with more bandwidth and less power
2023-2024 VLSI Mini Projects using Cadence
How to Design with Cadence:
Cadence Design Systems, Inc. is an American multinational electronic design automation (EDA) software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards. Cadence Design Systems was the result of a merger perfected in 1988 of Solomon Design Automation (SDA), co-founded in 1983 by Richard Newton, Alberto Sangiovanni-Vincentelli and James Solomon, and ECAD, co-founded by Glen Antle and Paul Huang in 1982. Joseph Costello was appointed as CEO from 1988–1997, and Cadence became the largest EDA company during his tenure.
2023-2024 VLSI Mini Projects using Mentor Graphics
Are You Ready with design with Mentor Graphics?
Mentor Graphics was founded in 1981 by Tom Bruggere, Gerry Langeler and Dave Moffenbeier. The first round of money, worth $1 million, came from Sutter Hill, Greylock, and Venrock Associates. The next round was $2 million from five venture capital firms, and in April 1983 a third round raised an additional $7 million. Mentor Graphics was one of the first companies to attract venture capital to Oregon.Apollo Computer workstations were chosen as the initial hardware platform. Based in Chelmsford, Apollo was less than a year old and had only announced itself to the public a few weeks prior to when the founders of Mentor Graphics began their initial meetings. When Mentor entered the CAE market the company had two technical differentiators: the first was the software - Mentor, Valid, and Daisy each had software with different strengths and weaknesses. The second, was the hardware - Mentor ran all programs on the Apollo workstation, while Daisy and Valid each built their own hardware. By the late 1980s, all EDA companies abandoned proprietary hardware in favor of workstations manufactured by companies such as Apollo and Sun Microsystems. 2021 vlsi projects abstracts pdf,2021 vlsi projects abstracts,2021 vlsi projects abstracts doc,ieee vlsi projects abstracts,vlsi mini projects abstracts,cmos vlsi mini projects,vlsi mini projects abstracts,vlsi based projects,vlsi based projects for final year,vlsi application based projects,vlsi projects for mtech,vlsi projects for mtech students,m.tech projects in vlsi /embedded systems,m.tech projects based on vlsi,m tech vlsi projects 2021,m tech vlsi projects 2022,vlsi projects ideas,vlsi projects for final year,vlsi projects list,best vlsi projects,projects on vlsi circuits,digital vlsi projects,vlsi related projects,vlsi related companies in bangalore,vlsi related companies in chennai,vlsi related companies in india,vlsi companies in chennai for freshers,vlsi openings for freshers,vlsi design mini projects,projects on vlsi technology,IEEE VLSI Project,2021 IEEE VLSI Projects,IEEE 2021 VLSI Projects,2022 IEEE VLSI Project,IEEE 2022 VLSI Project,vlsi projects chennai,matlab projects in chennai,Mechanical Projects,simulink projects,digital signal processing projects,Electronics projects,Power electronics Projects,wireless communication and networking projects Vlsi IEEE Projects 2023-2024, Vlsi IEEE Projects Titles 2023-2024. We are offering ieee projects 2023-2024 in latest technology like Java ieee projects, dotnet ieee projects, android ieee projects, embedded ieee projects, embedded diploma projects, matlab ieee projects, digital image processing ieee projects, dip ieee projects, vlsi ieee projects, hadoop ieee projects, big data ieee projects, power electronics ieee projects, power system ieee projects, mechanical final year projects, diploma mechanical projects, civil projects ieee projects. IEEE Master is a unit of LeMeniz Infotech. We guide all final year M.E/M.Tech, B.E/B.Tech, MPhil, MCA, BCA, M.Sc, B.Sc, and Diploma students for their Academic Projects to get best results. Download latest Vlsi IEEE Projects Titles 2023-2024
Are you really more interesting with this Matlab VLSI biomedical related projects?.Submit your applications today. So B tech and m tech Students can do their own Final year Engineering VLSI projects in bangalore with placement option and now most exciting Festival offers available for VLSI projects (Offer Valid upto December 2021)
For more Info Contact:9591912372
2023-2024 VLSI Projects
Projectsatbangalore, offers VLSI Projects to students in various areas like
IEEE 2024 VLSI PROJECTS
1. VLSI Implementation of an adaptive Edge Enhanced color interpolation Processor for Real-Time Video Applications
2. Demonstrating HW-SW Transient Error Mitigation on the single-chip cloud computer data plane
3. Enhanced Memory reliability against multiple cell upsets using Decimal Matrix code
4. Wear out Resilience in NOCs through an Aging Aware Adaptive Routing Algorithm
5. High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications On-Chip Memory Hierarchy in one Coarse-Grained Reconfigurable Architecture to compress memory space and to reduce time
6. A Voltage based Leakage current calculation scheme and its application to Nanoscale and FinFET Standard cell designs
7. High Throughput and Low complexity BCH decoding Architecture for Solid-State Drives
8. Nonbinary LDPC Decoder based on Simplified Enhanced Generalized Bit-Flipping Algorithm
9. A 2-D Interpolation based ORD Processor with Partial Layer Mapping for MIMO-OFDM Systems
10.Digitally controlled Pulse Width Modulator for On-Chip Power Management
11. UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors
12. High-Throughput Multistandard Transform Core supporting MPEG/H.264/VC-1 using Common Shared Distributed Arithmetic
13. Alogirthm and Architecture for a Low-Power Content Addressable Memory based on Sparse Clustered Networks
14. A Variation-Aware Preferential Design approach for Memory- Based Reconfigurable Computing
15. Asynchronous Domino Logic Pipeline Design Based on Constructed Critical data path
16. Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
17. Application Mapping Onto Mesh-Based Network-On-Chip using Discrete Particle Swarm Optimization
18. Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications
19. Single-Bit Pseudo Parallel Processing Low-oversampling Delta-Sigma Modulator suitable for SDR Wireless Transmitters
20. A Lattice Reduction Aided MIMO Channel Equalizer in 90 nm CMOS achieving 720 Mb/s
21. Low Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS Amplifiers
22. Low-Energy Two-stage Algorithm for High Efficiency Epileptic Seizure Detection
23. An Ultralow Power Multirate FSK Demodulator for High-Speed Biomedical Zero-IF Receivers
24. Ultra-High Throughput Low-Power Packet Classification
25. Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SOC's
26. Area-Delay-Power Efficient Fixed-point LMS Adaptive filter with low adaptation delay
27. Energy Efficiency Optimization through codesign of the Transmitter and Receiver in High-speed On-Chip Interconnects
28. A Fast application based supply voltage optimization method for dual voltage FPGA
29. Reliable Low-Power Multiplier Design using Fixed-Width Replica Redundancy block
30. Low-Power Pulse-Triggered Flip-Flop Design based on a signal feed-through
1. A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter For Sub-mW Energy Harvesting Applications
2. A Generalization Of Addition Chains And Fast Inversions In Binary Fields
3. A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of Dct
4. A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic
5. A Multicycle Test Set Based On A Two-Cycle Test Set With Constant Primary Input Vectors
6. A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems
7. A Synergetic Use Of Bloom Filters For Error Detection And Correction
8. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
9. Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks
10. An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm For Reconfigurable Fir Filter Synthesis
11. Comments On "Low-Latency Digit-Serial Systolic Double Basis Multiplier Over GF (2m ) Using Subquadrat Ic Toeplitz Matrix- Vector Product Approach"
12. Communication Optimization Of Iterative Sparse Matrix - Vector Multiply On GPUs And FPGAs
13. Efficient Coding Schemes For Fault-Tolerant Parallel Filters
14. Efficient Sub Quadratic Space Complexity Architectures For Parallel Mpb Single- And 16. For All Trinomials Using Toeplitz Matrix-Vector Product Decomposition
15. Fast Sign Detection Algorithm For The Rns Moduli Set {2n+1 - 1, 2n - 1,2n}
16. Fault Tolerant Parallel Filters Based On Error Correction Codes
17. Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications
18. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
19. Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For DSRC Applications
20. High - Throughput Finite Field Multipliers Using Redundant Basis For Fpga And Asic Implementations
21. Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes
22. Low-Complexity Tree Architecture For Finding The First Two Minima
23. Low-Latency High-Throughput Systolic Multipliers Over For Nist Recommended Pentanomials
24. Low-Power And Area-Efficient Shift Register Using Pulsed Latches
25. Low-Power Programmable PRPG With Test Compression Capabilities
26. Mixing Drivers In Clock-Tree For Power Supply Noise Reduction
27. New Regular Radix-8 Scheme For Elliptic Curve Scalar Multiplication Without Pre-Computation
28. Novel Block-Formulation And Area-Delay - Efficient Reconfigurable Interpolation Filter Architecture Formulti - Standard SDR Applications
29. Novel Shared Multiplier Scheduling Scheme For Area-Efficient FFT/IFFT Processors
30. Obfuscating DSP Circuits Via High-Level Transformations
31. One Minimum Only Trellis Decoder For Non – Binary Low - Density Parity - Check Codes
32. Partially Parallel Encoder Architecture For Long Polar Codes
33. Piecewise-Functional Broadside Tests Based On Reachable States
34. Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding
35. Recursive Approach To The Design Of A Parallel Self-Timed Adder
36. Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block
37. Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures
38. Simplified Trellis Min–Max Decoder Architecture For Nonbinary Low-Density Parity-Check Codes
39. Skewed-Load Test Cubes Based On Functional Broadside Tests For A Low-Power Test Set
40. VLSI Computational Architectures For The Arithmetic Cosine Transform
41. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
42. Graph-Based Transistor Network Generation Method for Supergate Design
43. High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design
44. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
45. High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule
46. Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application
47. In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
48. Integrating Lock-Free and Combining Techniques for a Practical and Scalable FIFO Queue
49. Learning Weighted Lower Linear Envelope Potentials in Binary Markov Random Fields
50. Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs
51. Long-Distance Measurement Applying Two High-Stability and Synchronous Wavelengths
52. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
53. MAC With Action-Dependent State Information at One Encoder
54. Minimum Parallel Binary Adders with NOR (NAND) Gates
55. Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder
56. Modulation Classification of Single-Input Multiple-Output Signals Using Asynchronous Sensors
57. Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications
58. Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System FIR Filter
59. Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications
60. Obfuscating DSP Circuits via High-Level Transformations
61. One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes
62. Partially Parallel Encoder Architecture for Long Polar Codes
63. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
64. Range Unlimited Delay-Interleaving and –Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit
65. Recursive Approach to the Design of a Parallel Self-Timed Adder
66. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
67. Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI
68. Shift Register Design Using Two Bit Flip-Flop
69. Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent Reception
70. Synthesis of Genetic Clock with Combinational Biologic Circuits
71. Timing Error Tolerance in Small Core Designs for SoC Applications
72. Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters FIR Filter
73. VLSI-Assisted Non-rigid Registration Using Modified Demons Algorithm
1.A Bit-Plane Decomposition Matrix-Based VLSI Integer Transform Architecture for HEVC
2.Probability-Driven Multibit Flip-Flop Integration With Clock Gating
3.Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication
4.Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA
5.Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction
6.A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits
7.Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit
8.Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials
9.Probabilistic Error Modeling for Approximate Adders
10.LFSR-Based Generation of Multicycle Tests
11.Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs
12.An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA
13.RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
14.DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
15.A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
16.Design of Efficient Multiplierless Modified Cosine-Based Comb Decimation Filters: Analysis and Implementation
17.Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping
18.Design of Efficient BCD Adders in Quantum-Dot Cellular Automata
19.Overloaded CDMA Crossbar for Network-On-Chip
20.High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
21.Design of Power and Area Efficient Approximate Multipliers
22.An Efficient O(N) Comparison-Free Sorting Algorithm
23.Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems
24.A General Digit-Serial Architecture for Montgomery Modular Multiplication
25.High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
26.Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
27.Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
28.A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes
29.On the VLSI Energy Complexity of LDPC Decoder Circuits
30.Reconfigurable Constant Multiplication for FPGAs
31.LLR-Based Successive-Cancellation List Decoder for Polar Codes With Multibit Decision
32.Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division
33.Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields
34.Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
35.Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique
36.Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders
37.Register-Less NULL Convention Logic
38.Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops
39.Delay Analysis for Current Mode Threshold Logic Gate Designs
40.10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
41.A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model
42.A Hardware-Software Co-designed AES-ECC Cryptosystem
43.A Uniquified Virtualization Approach to Hardware Security
44.Compact Constant Weight Coding Engines for the Code Based Cryptography
45.Construction of Rotation Symmetric S-Boxes with High Nonlinearity and Improved DPA Resistivity
46.Classification of Error Correcting Codes and Estimation of Interleaver Parameters in a Noisy Transmission Environment
47.Design and Applications for Embedded Networks-on-Chip on FPGAs
48.Overloaded CDMA Crossbar for Network-On-Chip
49.Design and Validation for FPGA Trust under Hardware Trojan Attacks
50.High-Speed and Low-Latency ECC Processor Implementation Over GF(2 m ) on FPGA
51.LAXY: A Location-Based Aging-Resilient Xy-Yx Routing Algorithm for Network on Chip
52.FoToNoC: A Folded Torus-Like Network-on-Chip based Many-Core Systems-on-Chip in the Dark Silicon Era
53.Lightweight Hardware Architectures for the Present Cipher in FPGA
54.Multipartite entangled states, symmetric matrices and error-correcting codes
55.Designing an FPGA-Accelerated Homomorphic Encryption Co-Processor
56.Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves
57.A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
58.Adaptive Multi-bit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication
59.Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture
60.Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
61.A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption
62.Resource-Efficient SRAM-based Ternary Content Addressable Memory
63.Write-Amount-Aware Management Policies for STT-RAM Caches
64.Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA
65.High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
66.High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
67.Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
68.Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map
69.Efficient Designs of Multi-ported Memory on FPGA
70.High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
71.An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock
72.A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique
73.Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares
74.Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm
75.A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission
76.Scalable Device Array for Statistical Characterization of BTI-Related Parameters
77.VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding
78.A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical Bits
79.ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware
80.Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs
81.Efficient Soft Cancelation Decoder Architectures for Polar Codes
82.Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition
83.Hybrid LUT Multiplexer FPGA Logic Architectures
84.Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
85.FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers
86.Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields
87.Antiwear Leveling Design for SSDs With Hybrid ECC Capability
88.Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems
89.A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding
90.Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations
91.Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
92.An FPGA-Based Hardware Accelerator for Traffic Sign Detection
93.Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations
94.Time-Encoded Values for Highly Efficient Stochastic Circuits
95.Design of Power and Area Efficient Approximate Multipliers
96.COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits
97.Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction
98.Multicast-Aware High-Performance Wireless Network-on-Chip Architectures
For VLSI FPGA IEEE 2023-2024 Project Titles Contact:9591912372
2023-2024 VLSI Projects
Projectsatbangalore, offers VLSI Projects to students in various areas like
2023-2024 VLSI Final Year IEEE Projects
1. VLSI Implementation of an adaptive Edge Enhanced color interpolation Processor for Real-Time Video Applications
2. Demonstrating HW-SW Transient Error Mitigation on the single-chip cloud computer data plane
3. Enhanced Memory reliability against multiple cell upsets using Decimal Matrix code
4. Wear out Resilience in NOCs through an Aging Aware Adaptive Routing Algorithm
5. High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications On-Chip Memory Hierarchy in one Coarse-Grained Reconfigurable Architecture to compress memory space and to reduce time
6. A Voltage based Leakage current calculation scheme and its application to Nanoscale and FinFET Standard cell designs
7. High Throughput and Low complexity BCH decoding Architecture for Solid-State Drives
8. Nonbinary LDPC Decoder based on Simplified Enhanced Generalized Bit-Flipping Algorithm
9. A 2-D Interpolation based ORD Processor with Partial Layer Mapping for MIMO-OFDM Systems
10.Digitally controlled Pulse Width Modulator for On-Chip Power Management
2023-2024 Final Year VLSI Projects
11. UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors
12. High-Throughput Multistandard Transform Core supporting MPEG/H.264/VC-1 using Common Shared Distributed Arithmetic
13. Alogirthm and Architecture for a Low-Power Content Addressable Memory based on Sparse Clustered Networks
14. A Variation-Aware Preferential Design approach for Memory- Based Reconfigurable Computing
15. Asynchronous Domino Logic Pipeline Design Based on Constructed Critical data path
16. Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
17. Application Mapping Onto Mesh-Based Network-On-Chip using Discrete Particle Swarm Optimization
18. Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications
19. Single-Bit Pseudo Parallel Processing Low-oversampling Delta-Sigma Modulator suitable for SDR Wireless Transmitters
20. A Lattice Reduction Aided MIMO Channel Equalizer in 90 nm CMOS achieving 720 Mb/s
21. Low Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS Amplifiers
22. Low-Energy Two-stage Algorithm for High Efficiency Epileptic Seizure Detection
23. An Ultralow Power Multirate FSK Demodulator for High-Speed Biomedical Zero-IF Receivers
24. Ultra-High Throughput Low-Power Packet Classification
25. Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SOC's
26. Area-Delay-Power Efficient Fixed-point LMS Adaptive filter with low adaptation delay
27. Energy Efficiency Optimization through codesign of the Transmitter and Receiver in High-speed On-Chip Interconnects
28. A Fast application based supply voltage optimization method for dual voltage FPGA
29. Reliable Low-Power Multiplier Design using Fixed-Width Replica Redundancy block
30. Low-Power Pulse-Triggered Flip-Flop Design based on a signal feed-through
2023-2024 VLSI Projects using Verilog
1. A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter For Sub-mW Energy Harvesting Applications
2. A Generalization Of Addition Chains And Fast Inversions In Binary Fields
3. A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of Dct
4. A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic
5. A Multicycle Test Set Based On A Two-Cycle Test Set With Constant Primary Input Vectors
6. A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems
7. A Synergetic Use Of Bloom Filters For Error Detection And Correction
8. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
9. Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks
10. An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm For Reconfigurable Fir Filter Synthesis
11. Comments On "Low-Latency Digit-Serial Systolic Double Basis Multiplier Over GF (2m ) Using Subquadrat Ic Toeplitz Matrix- Vector Product Approach"
12. Communication Optimization Of Iterative Sparse Matrix - Vector Multiply On GPUs And FPGAs
13. Efficient Coding Schemes For Fault-Tolerant Parallel Filters
14. Efficient Sub Quadratic Space Complexity Architectures For Parallel Mpb Single- And 16. For All Trinomials Using Toeplitz Matrix-Vector Product Decomposition
2023-2024 VLSI Projects using VHDL
15. Fast Sign Detection Algorithm For The Rns Moduli Set {2n+1 - 1, 2n - 1,2n}
16. Fault Tolerant Parallel Filters Based On Error Correction Codes
17. Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications
18. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
19. Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For DSRC Applications
20. High - Throughput Finite Field Multipliers Using Redundant Basis For Fpga And Asic Implementations
21. Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes
22. Low-Complexity Tree Architecture For Finding The First Two Minima
23. Low-Latency High-Throughput Systolic Multipliers Over For Nist Recommended Pentanomials
24. Low-Power And Area-Efficient Shift Register Using Pulsed Latches
25. Low-Power Programmable PRPG With Test Compression Capabilities
26. Mixing Drivers In Clock-Tree For Power Supply Noise Reduction
27. New Regular Radix-8 Scheme For Elliptic Curve Scalar Multiplication Without Pre-Computation
28. Novel Block-Formulation And Area-Delay - Efficient Reconfigurable Interpolation Filter Architecture Formulti - Standard SDR Applications
29. Novel Shared Multiplier Scheduling Scheme For Area-Efficient FFT/IFFT Processors
30. Obfuscating DSP Circuits Via High-Level Transformations
31. One Minimum Only Trellis Decoder For Non – Binary Low - Density Parity - Check Codes
32. Partially Parallel Encoder Architecture For Long Polar Codes
33. Piecewise-Functional Broadside Tests Based On Reachable States
34. Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding
35. Recursive Approach To The Design Of A Parallel Self-Timed Adder
36. Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block
37. Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures
38. Simplified Trellis Min–Max Decoder Architecture For Nonbinary Low-Density Parity-Check Codes
39. Skewed-Load Test Cubes Based On Functional Broadside Tests For A Low-Power Test Set
40. VLSI Computational Architectures For The Arithmetic Cosine Transform
41. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
42. Graph-Based Transistor Network Generation Method for Supergate Design
43. High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design
44. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
45. High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule
2023-2024 VLSI Projects using Verilog
46. Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application
47. In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
48. Integrating Lock-Free and Combining Techniques for a Practical and Scalable FIFO Queue
49. Learning Weighted Lower Linear Envelope Potentials in Binary Markov Random Fields
50. Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs
51. Long-Distance Measurement Applying Two High-Stability and Synchronous Wavelengths
52. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
53. MAC With Action-Dependent State Information at One Encoder
54. Minimum Parallel Binary Adders with NOR (NAND) Gates
55. Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder
56. Modulation Classification of Single-Input Multiple-Output Signals Using Asynchronous Sensors
57. Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications
58. Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System FIR Filter
59. Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications
2023-2024 m.tech VLSI Projects
60. Obfuscating DSP Circuits via High-Level Transformations
61. One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes
62. Partially Parallel Encoder Architecture for Long Polar Codes
63. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
64. Range Unlimited Delay-Interleaving and –Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit
65. Recursive Approach to the Design of a Parallel Self-Timed Adder
66. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
67. Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI
68. Shift Register Design Using Two Bit Flip-Flop
69. Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent Reception
70. Synthesis of Genetic Clock with Combinational Biologic Circuits
71. Timing Error Tolerance in Small Core Designs for SoC Applications
72. Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters FIR Filter
73. VLSI-Assisted Non-rigid Registration Using Modified Demons Algorithm
2023-2024 VLSI Projects using Mentor Graphics
1.A Bit-Plane Decomposition Matrix-Based VLSI Integer Transform Architecture for HEVC
2.Probability-Driven Multibit Flip-Flop Integration With Clock Gating
3.Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication
4.Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA
5.Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction
6.A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits
7.Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit
8.Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials
9.Probabilistic Error Modeling for Approximate Adders
10.LFSR-Based Generation of Multicycle Tests
11.Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs
12.An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA
13.RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
14.DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
15.A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
16.Design of Efficient Multiplierless Modified Cosine-Based Comb Decimation Filters: Analysis and Implementation
17.Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping
18.Design of Efficient BCD Adders in Quantum-Dot Cellular Automata
19.Overloaded CDMA Crossbar for Network-On-Chip
20.High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
21.Design of Power and Area Efficient Approximate Multipliers
22.An Efficient O(N) Comparison-Free Sorting Algorithm
23.Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems
24.A General Digit-Serial Architecture for Montgomery Modular Multiplication
25.High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
26.Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
27.Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
28.A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes
29.On the VLSI Energy Complexity of LDPC Decoder Circuits
30.Reconfigurable Constant Multiplication for FPGAs
31.LLR-Based Successive-Cancellation List Decoder for Polar Codes With Multibit Decision
32.Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division
33.Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields
34.Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
35.Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique
36.Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders
37.Register-Less NULL Convention Logic
38.Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops
39.Delay Analysis for Current Mode Threshold Logic Gate Designs
40.10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
41.A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model
42.A Hardware-Software Co-designed AES-ECC Cryptosystem
43.A Uniquified Virtualization Approach to Hardware Security
44.Compact Constant Weight Coding Engines for the Code Based Cryptography
45.Construction of Rotation Symmetric S-Boxes with High Nonlinearity and Improved DPA Resistivity
46.Classification of Error Correcting Codes and Estimation of Interleaver Parameters in a Noisy Transmission Environment
47.Design and Applications for Embedded Networks-on-Chip on FPGAs
48.Overloaded CDMA Crossbar for Network-On-Chip
49.Design and Validation for FPGA Trust under Hardware Trojan Attacks
50.High-Speed and Low-Latency ECC Processor Implementation Over GF(2 m ) on FPGA
51.LAXY: A Location-Based Aging-Resilient Xy-Yx Routing Algorithm for Network on Chip
52.FoToNoC: A Folded Torus-Like Network-on-Chip based Many-Core Systems-on-Chip in the Dark Silicon Era
53.Lightweight Hardware Architectures for the Present Cipher in FPGA
54.Multipartite entangled states, symmetric matrices and error-correcting codes
55.Designing an FPGA-Accelerated Homomorphic Encryption Co-Processor
56.Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves
57.A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
58.Adaptive Multi-bit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication
59.Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture
60.Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
61.A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption
62.Resource-Efficient SRAM-based Ternary Content Addressable Memory
63.Write-Amount-Aware Management Policies for STT-RAM Caches
64.Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA
65.High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
66.High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
67.Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
68.Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map
69.Efficient Designs of Multi-ported Memory on FPGA
70.High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
71.An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock
72.A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique
73.Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares
74.Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm
75.A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission
76.Scalable Device Array for Statistical Characterization of BTI-Related Parameters
77.VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding
78.A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical Bits
79.ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware
80.Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs
81.Efficient Soft Cancelation Decoder Architectures for Polar Codes
82.Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition
83.Hybrid LUT Multiplexer FPGA Logic Architectures
84.Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
85.FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers
86.Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields
87.Antiwear Leveling Design for SSDs With Hybrid ECC Capability
88.Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems
89.A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding
90.Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations
91.Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
92.An FPGA-Based Hardware Accelerator for Traffic Sign Detection
93.Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations
94.Time-Encoded Values for Highly Efficient Stochastic Circuits
95.Design of Power and Area Efficient Approximate Multipliers
96.COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits
97.Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction
98.Multicast-Aware High-Performance Wireless Network-on-Chip Architectures
For VLSI FPGA IEEE 2023-2024 Project Titles Contact:9591912372
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