Ai On Esp32 | AI Final Year Project Report

Complete Technical Paper Content — Ai On Esp32

1. Executive Abstract, Problem Formulation & Background

RISC-V (pronounced "risk-five") is a free and open standard instruction set architecture (ISA) for computer CPUs. It is based on reduced instruction set computer (RISC) principles. Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented without paying royalties. RISC-V was developed in 2010 at the University of California, Berkeley as the fifth generation of RISC processors created at the university since 1981. In 2015, development and maintenance of the standard was transferred to RISC-V International, a non-profit organization based in Switzerland with more than 4,500 members as of 2025. RISC-V is a popular architecture for microcontrollers and embedded systems, with development of higher-performance implementations targeting mobile, desktop, and server markets ongoing. The ISA is supported by several major Linux distributions, and companies such as SiFive, Andes Technology, SpacemiT, Synopsys, Alibaba (DAMO Academy), StarFive, Espressif Systems, and Raspberry Pi offer commercial systems on a chip (SoCs) and microcontrollers (MCUs) that incorporate one or more RISC-V compatible processor cores.

The RISC-V authors and their institution originally sourced the ISA documents and several CPU designs under BSD licenses, which allow derivative works—such as RISC-V chip designs—to be either open and free, or closed and proprietary. The ISA specification itself (i.e., the encoding of the instruction set) was published in 2011 as open source, with all rights reserved. The actual technical report (an expression of the specification) was later placed under the license Creative Commons - Attribution 4.0 to permit enhancement by external contributors through the RISC-V Foundation, and later RISC-V International. A full history of RISC-V has been published on the RISC-V International website.

CPU design requires design expertise in several specialties: electronic digital logic, compilers, and operating systems. To cover the costs of such a team, commercial vendors of processor intellectual property (IP), such as Arm Ltd. and MIPS Technologies, charge royalties for the use of their designs and patents. They also often require non-disclosure agreements before releasing documents that describe their designs' detailed advantages. In many cases, they never describe the reasons for their design choices. RISC-V was begun with a goal to make a practical ISA that was open-sourced, usable academically, and deployable in any hardware or software design without royalties. Also, justifying rationales for each design decision of the project are explained, at least in broad terms. The RISC-V authors are academics who have substantial experience in computer design, and the RISC-V ISA is a direct development from a series of academic computer-design projects, especially Berkeley RISC. RISC-V was originated in part to aid all such projects. To support a broad range of applications and implementations, the RISC-V ISA supports compact, high-performance, and low-power implementations without being tailored to a specific microarchitecture. The designers' primary assertion is that the instruction set is the key interface in a computer as it is situated at the interface between the hardware and the software. If a good instruction set were open and available for use by all, then it can dramatically reduce the cost of software by enabling far more reuse. It should also trigger increased competition among hardware providers, who can then devote more resources toward design and less for software support. The designers maintain that new principles are becoming rare in instruction set design, as the most successful designs of the last forty years have grown increasingly similar. Of those that failed, most did so because their sponsoring companies were financially unsuccessful, not because the instruction sets were technically poor. Thus, a well-designed open instruction set designed using well-established principles should attract long-term support by many vendors. RISC-V also encourages academic usage. The simplicity of the integer subset permits basic student exercises, and is a simple enough ISA to enable software to control research machines. The variable-length ISA provides room for instruction set extensions for both student exercises and research, and the separated privileged instruction set permits research in operating system support without redesigning compilers. RISC-V's open intellectual property paradigm allows derivative designs to be published, reused, and modified.

2. Related Work, Literature Survey & Algorithmic Foundations

The standard extensions are specified to work with all of the standard bases, and with each other without conflict. Many RISC-V computers might implement the compressed instructions extension, C, to reduce power consumption, code size, and memory use. RISC-V processors may implement the H extension, which provides hardware support for hypervisors and virtualization. Additional extensions continue to expand and improve RISC-V's virtualization capabilities. Together with the S supervisor extension, an RVG instruction set, which includes one of the RV base instruction sets and the G collection of extensions (which includes "I", meaning that the base is non-embedded), defines all instructions needed to conveniently support a general purpose operating system.

To name the combinations of functions that may be implemented, a nomenclature is defined to specify them in Chapter 27 of the current ratified Unprivileged ISA Specification. The instruction set base is specified first, coding for RISC-V, the register bit-width, and the variant; e.g., RV64I or RV32E. Then follows letters specifying implemented extensions, in the order of the above table. Each letter may be followed by a major optionally followed by "p" and a minor option number. It defaults to 0 if a minor version number is absent, and 1.0 if all of a version number is absent. Thus RV64IMAFD may be written as RV64I1p0M1p0A1p0F1p0D1p0 or more simply as RV64I1M1A1F1D1. Underscores may be used between extensions for readability, for example RV32I2_M2_A2.

The base, extended integer & floating-point calculations, with synchronization primitives for multi-core computing, are considered to be necessary for general-purpose computing, and are represented with the shorthand, "G". A small 32-bit computer for an embedded system might be RV32EC. A large 64-bit computer might be RV64GC; i.e., RV64IMAFDCZicsr_Zifencei. With the growth in the number of extensions, the standard now provides for extensions to be named by a single "Z" followed by an alphabetical name and an optional version number. For example, Zifencei names the instruction-fetch extension. Zifencei2 and Zifencei2p0 name version 2.0 of the same. The first letter following the "Z" by convention indicates the most closely related alphabetical extension category, IMAFDQLCBJTPVN. Thus the Zam extension for misaligned atomics relates to the "A" standard extension. Unlike single character extensions, Z extensions must be separated by underscores, grouped by category and then alphabetically within each category. For example, Zicsr_Zifencei_Zam. Extensions specific to supervisor privilege level are named in the same way using "S" for prefix. Extensions specific to hypervisor level are named using "H" for prefix. Machine level extensions are prefixed with the three letters "Zxm". Supervisor, hypervisor and machine level instruction set extensions are named after less privileged extensions. RISC-V developers may create their own non-standard instruction set extensions. These follow the "Z" naming convention, but with "X" as the prefix. They should be specified after all standard extensions, and if multiple non-standard extensions are listed, they should be listed alphabetically.

3. Dataset Ingestion, Preprocessing & Stochastic Augmentations

This flexibility can be used to highly optimize a specialized design by including only the exact set of ISA features required for an application, but the same flexibility also leads to a combinatorial explosion in possible ISA choices. Profiles specify a much smaller common set of ISA choices that capture the most value for most users, and which thereby enable the software community to focus resources on building a rich software ecosystem. The platform specification defines a set of platforms that specify requirements for interoperability between software and hardware. The Platform Policy defines the various terms used in this platform specification. The platform policy also provides the needed detail regarding the scope, coverage, naming, versioning, structure, life cycle and compatibility claims for the platform specification. The RISC-V Profiles RVI20, RVA20, RVA22 are version 1.0 as at March 2023. The RVA23 and RVB23 Profiles are version 1.0 as at October 2024. RVA23U64 makes the V Vector extensions mandatory, it was optional in RVA22U64.

RISC-V has 32 integer registers (or 16 in the embedded variant), and when the floating-point extension is implemented, an additional 32 floating-point registers. Except for memory access instructions, instructions address only registers. The first integer register is a zero register, and the remainder are general-purpose registers. A store to the zero register has no effect, and a read always provides 0. Using the zero register as a placeholder makes for a simpler instruction set. Control and status registers exist, but user-mode programs can access only those used for performance measurement and floating-point management. No instructions exist to save and restore multiple registers. Those were thought to be needless, too complex, and perhaps too slow.

Systems that have only machine mode, perhaps for simple embedded systems, Systems with both machine mode (for a simple supervisor) and user-mode to implement relatively secure embedded systems, Systems with machine-mode, supervisor mode (for operating system) and user-modes for typical operating systems. These correspond roughly to systems with up to four ‘’rings’’ of privilege and security, at most: machine, hypervisor, supervisor and user. Each layer also is expected to have a thin layer of standardized supporting software that communicates to a more-privileged layer, or hardware. The ISA also includes a hypervisor mode that is orthogonal to the user and supervisor modes. The basic feature is a configuration bit that either permits supervisor-level code to access hypervisor registers, or causes an interrupt on accesses. This bit lets supervisor mode directly handle the hardware needed by a hypervisor. This simplifies the implementation of hypervisors that are hosted by an operating system. This is a popular mode to run warehouse-scale computers. To support non-hosted hypervisors, the bit can cause these accesses to interrupt to a hypervisor. The design also simplifies nesting of hypervisors, in which a hypervisor runs under a hypervisor, and if necessary it lets the kernel use hypervisor features within its own kernel code. As a result, the hypervisor form of the ISA supports five modes: machine, supervisor, user, supervisor-under-hypervisor and user-under-supervisor. The privileged instruction set specification explicitly defines hardware threads, or harts. Multiple hardware threads are a common practice in more-capable computers. When one thread is stalled, waiting for memory, others can often proceed. Hardware threads can help make better use of the large number of registers and execution units in fast out-of-order CPUs. Finally, hardware threads can be a simple, powerful way to handle interrupts: No saving or restoring of registers is required, simply executing a different hardware thread. However, the only hardware thread required in a RISC-V computer is thread zero. Interrupts and exceptions are handled together. Exceptions are caused by instruction execution including illegal instructions and system calls, while interrupts are caused by external events. The existing control and status register definitions support RISC-V's error and memory exceptions, and a small number of interrupts, typically via an "advanced core local interruptor" (ACLINT). For systems with more interrupts, the specification also defines a platform-level interrupt controller (PLIC) to coordinate large number of interrupts among multiple processors. Interrupts always start at the highest-privileged machine level, and the control registers of each level have explicit forwarding bits to route interrupts to less-privileged code. For example, the hypervisor need not include software that executes on each interrupt to forward an interrupt to an operating system. Instead, on set-up, it can set bits to forward the interrupt. Several memory systems are supported in the specification. Physical-only is suited to the simplest embedded systems. There are also four UNIX-style virtual memory systems for memory cached in mass-storage systems. The virtual memory systems support MMU with four sizes, with addresses sized 32, 39, 48 and 57 bits. All virtual memory systems support 4 KiB pages, multilevel page-table trees and use very similar algorithms to walk the page table trees. All are designed for either hardware or software page-table walking. To optionally reduce the cost of page table walks, super-sized pages may be leaf pages in higher levels of a system's page table tree. SV32 is only supported on 32-bit implementations, has a two-layer page table tree and supports 4 MiB superpages. SV39 has a three level page table, and supports 2 MiB superpages and 1 GiB gigapages. SV48 is required to support SV39. It also has a 4-level page table and supports 2 MiB superpages, 1 GiB gigapages, and 512 GiB terapages. SV57 has a 5-level page table and supports 2 MiB superpages, 1 GiB gigapages, 512 GiB terapages and 256 TiB petapages. Superpages are aligned on the page boundaries for the next-lowest size of page.

4. Neural Network Backbone, Layer Specifications & Loss Formulations

Akeana of Santa Clara, CA, a Premier member of RISC-V International, offers a wide range of RISC-V-based IP. Its offerings range from tiny 32-bit cores to advanced datacenter-class 64-bit cores with FPU, Vector, Hypervisor, and multicore capabilities, as well as IOMMU, high-speed interconnect fabric, AI accelerators, and related IP. Andes Technology Corporation of Hsinchu, Taiwan, a Founding Premier member of RISC-V International. Its RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, vector, superscalar, and/or multicore capabilities. Bouffalo Lab has a series of MCUs based on RISC-V (RV32IMACF, BL60x/BL70x series). CloudBEAR is a processor IP company that develops its own RISC-V cores for a range of applications. Codasip of Munich, Germany, a founding member of RISC-V International, started developing a range of low-power embedded, high-performance embedded and application processor cores in 2015. In 2016, Codasip and UltraSoC developed fully supported intellectual property for RISC-V embedded SOCs that combine Codasip's RISC-V cores and other IP with UltraSoC's debug, optimization and analytics. Cortus of Mauguio in the Montpellier area, France, is an original founding Platinum member of the RISC-V foundation and the RISC-V International. The company offers several RISC-V implementations. Cortus offers ASIC design services using its IP portfolio including RISC-V 32/64-bit processors from low-end to very high performance RISC-V processors, digital, analog, RF, security and a complete IDE/toolchain/debug eco-system. Espressif of Shanghai, China, added a RISC-V ULP coprocessor to their ESP32-S2 microcontroller. In November 2020 Espressif announced its ESP32-C3, a single-core, 32-bit, RISC-V-based MCU (RV32IMC). The Fraunhofer Institute for Photonic Microsystems, based in Dresden, Germany, was the first organization to develop a RISC-V core that can meet functional safety requirements. The IP Core EMSA5 is a 32-bit processor with a five-stage pipeline and is available as a general purpose variant (EMSA5-GP) and as a safety variant (EMSA5-FS) that can meet an ISO 26262 Automotive Safety Integrity Level-D standard. GigaDevice of Beijing, China, developed a series of MCUs based on RISC-V (RV32IMAC, GD32V series) in 2019, with one of them used on the Longan Nano board produced by a Chinese electronic company Sipeed. Google has developed the Titan M2 security module for the Pixel 6 and Pixel 7. GreenWaves Technologies announced the availability of GAP8, a 32-bit 1 controller plus 8 compute cores, 32-bit SoC (RV32IMC) and developer board in February 2018. Their GAPuino GAP8 development board started shipping in May 2018. Imagination Technologies of Kings Langley, England, UK, released the RTXM-2200 in 2023, their first core from their Catapult range. This is a real-time, deterministic, 32-bit embedded CPU. Instant SoC RISC-V cores from FPGA cores. System on chip, including RISC-V cores, defined by C++. Micro Magic Inc. announced the world's fastest 64-bit RISC-V core achieving 5 GHz and 13 000 CoreMarks in October 2020. MIPS Technologies of San Jose, California, pivoted to developing RISC-V cores in 2021. It rolled out its first implementation eVocore P8700 in December 2022. Nordic Semiconductor has announced its nRF54H20 family of Bluetooth radio chips that include multiple RISC-V coprocessor cores in addition to their more-usual ARM cores. Nvidia has used RISC-V in place of its proprietary Falcon microcontrollers since 2016, and they reported shipping over a billion RISC-V cores across its products in 2024. Seagate, in December 2020, announced that it had developed two RISC-V general-purpose cores for use in upcoming controllers for its storage devices. StarFive, (initially an exclusive distributor of SiFive RISC-V core IP products in the greater China region) of Shanghai, China, offers two RISC-V implementations – one for big data applications and the other for computational storage. Syntacore, a founding member of RISC-V International and one of the first commercial RISC-V IP vendors, develops and licenses family of RISC-V IP since 2015. As of 2018, product line includes eight 32- and 64-bit cores, including open-source SCR1 MCU core (RV32I/E[MC]). First commercial SoCs, based on the Syntacore IP were demonstrated in 2016. WinChipHead (WCH), a Chinese semiconductor manufacturer of popular and inexpensive USB chips such as CH340 and ARM microcontrollers introduced a simple, inexpensive RISC-V microcontroller line CH32Vxxx, headed by US$0.10 CH32V003. As of 2020, the Indian defence and strategic sector started using the 64-bit RISC-V based 100–350 MHz Risecreek processor developed by IIT Madras which is fabricated by Intel with 22 nm FinFET process. IIT Madras and ISRO Inertial Systems Unit successfully designed and booted a 64-bit RISC-V Controller for Space Applications (IRIS) chip based on the SHAKTI baseline processor in February 2025. The chip configuration takes into account the processing power and functional needs of the devices and sensors utilized in ISRO missions. To improve dependability, fault-tolerant internal memory were interfaced with the SHAKTI core. RIES v3.0d development boards are the first to use DIR-V VEGA RISC-V processors. It contains the VEGA ET1031, a 32-bit RISC-V CPU with three UART serial ports, four Serial Peripheral Interface ports, two megabytes of flash memory, 256KB of SRAM, and three 32-bit timers. It operates at 100 MHz. It is advised for usage in wearables, toys, small IoT devices, and sensors by C-DAC in Indian market. For efficiency and multitasking capabilities in consumer electronics, automotive systems, 5G infrastructure, industrial automation, and the IoT, C-DAC introduced the dual-core 1.0 GHz DHRUV RISC-V 64-bit processor in 2025 using 28 nm process.

ASTC developed a RISC-V CPU for embedded ICs. Centre for Development of Advanced Computing (C-DAC) in India is developing a single core 32-bit in-order, a single core 64-bit in-order and three out-of-order single, dual and quad-core RISC-V processor under VEGA Microprocessors series. Cobham Gaisler NOEL-V 64-bit. Computer Laboratory, University of Cambridge, in collaboration with the FreeBSD Project, has ported that operating system to 64-bit RISC-V to use as a hardware-software research platform. Esperanto Technologies announced that they are developing three RISC-V based processors: the ET-Maxion high-performance core, ET-Minion energy-efficient core, and ET-Graphics graphics processor. Esperanto ET-SoC-1, a 200 TOPS "kilocore" supercomputer on a chip, with 1088 small 64-bit in-order ET-Minion cores with tensor/vector units and 4 big 64-bit out-of-order ET-Maxion cores ETH Zurich and the University of Bologna have cooperatively developed the open-source RISC-V PULPino processor as part of the Parallel Ultra-Low Power (PULP) project for energy-efficient IoT computing. European Processor Initiative (EPI), RISC-V Accelerator Stream. Reconfigurable Intelligent Systems Engineering Group (RISE) of IIT-Madras is developing six Shakti series RISC-V open-source CPU designs for six distinct uses, from a small 32-bit CPU for the Internet of things (IoT) to large, 64-bit CPUs designed for warehouse-scale computers such as server farms based on RapidIO and Hybrid Memory Cube technologies. 32-bit Moushik successfully booted by RISE for the application of credit cards, electronic voting machines (EVMs), surveillance cameras, safe locks, personalized health management systems. lowRISC is a non profit project to implement a fully open-source hardware system on a chip (SoC) based on the 64-bit RISC-V ISA. RV64X consortium is working on a set of graphics extensions to RISC-V and has announced that they are developing an open source RISC-V core with a GPU unit. Ventana Micro Systems revealed it is developing high performance RISC-V CPU IP and chiplet technology targeting data center applications.

In 2022, ClockworkPi released two hobbyist computing kits, the DevTerm terminal and uConsole handheld computer. Both kits offered a single core 64-bit RISC-V module as an option, using the RV64IMAFDCVU based on the Allwinner D1 SoC. DeepComputing, a hardware company based in Hong Kong, announced the release on 13 April 2023 of the "world's first laptop with RISC-V processor"; the notebook, called "DC-ROMA", was delivered to its first customers in August 2023 and came pre-installed with the Chinese openKylin Linux operating system. The device's basic model, available from Alibaba, was still expensive at roughly US$1500 considering it was powered by the relatively slow Alibaba (DAMO) CPU "XuanTie C910". An upgrade in June 2024 doubled the core count to 8 cores and increased the clock speed to 2 GHz (from 1.5 GHz), while dropping the price to US$1,000. The processor used was a SpacemiT SoC K1. A collaboration with Canonical meant that the ROMA II came pre-installed with the major international Linux distribution Ubuntu. In 2024, DeepComputing announced a collaboration with Framework Computer to produce a mainboard for its Framework Laptop 13. On 4 February 2025 the laptop was ready to ship; it was mainly targeted at developers. It features a 4-core StarFive JH7110 processor. In 2025, DeepComputing announced DC-ROMA AI PC, a second mainboard for the Framework Laptop 13. Its based on ESWIN's EIC7702X SoC that has AI capabilities up to 50 TOPS when NPU (Neural Processing Unit) is enabled.

5. Training Protocol, Convergence Behavior & Experimental Evaluation

A brain–computer interface (BCI), sometimes called a brain–machine interface (BMI), is a system that measures brain activity and translates it into functionally useful outputs, allowing interaction with an external or internal system, most commonly a computer or robotic limb. BCIs are often directed at researching, mapping, assisting, augmenting, or repairing human cognitive or sensory-motor functions. Due to the cortical plasticity of the brain, signals from implanted prostheses can, after adaptation, be handled by the brain like natural sensor or effector channels. They are often conceptualized as a human–machine interface that skips the intermediary of moving body parts (e.g. hands or feet). BCI implementations range from non-invasive (EEG, MEG, MRI) and partially invasive (ECoG and endovascular) to invasive (microelectrode array) based on how physically close electrodes are to brain tissue. Research on BCIs began in the 1970s by Jacques Vidal at the University of California, Los Angeles (UCLA) under a grant from the National Science Foundation. This was followed by a contract from the Defense Advanced Research Projects Agency (DARPA) that prompted further research into the technology. Vidal's 1973 paper introduced the expression brain–computer interface into scientific literature. Following years of animal experimentation, the first neuroprosthetic devices were implanted in humans in the mid-1990s

Neuroprosthetics is an area of neuroscience concerned with neural prostheses, that is, using artificial devices to replace the function of impaired nervous systems and brain-related problems, or of sensory or other organs (bladder, diaphragm, etc.). As of December 2010, cochlear implants, the first neuroprosthetic device, had been implanted in some 736,900 people worldwide. Other neuroprosthetic devices aim to restore vision, including retinal implants. The terms are sometimes used interchangeably. Neuroprosthetics and BCIs seek to achieve the same aims, such as restoring sight, hearing, movement, ability to communicate, and even cognitive function. Both use similar experimental methods and surgical techniques.

Several laboratories have managed to read signals from monkey and rat cerebral cortices to operate BCIs to produce movement. Monkeys have moved computer cursors and commanded robotic arms to perform simple tasks simply by thinking about the task and seeing the results, without motor output. In May 2008 photographs that showed a monkey at the University of Pittsburgh Medical Center operating a robotic arm by thinking were published in multiple studies. Sheep have also been used to evaluate BCI technology, including Synchron's Stentrode and Paradromics' Connexus BCI. In 2020, Elon Musk's Neuralink was successfully implanted in a pig. In 2021, Musk announced that the company had successfully enabled a monkey to play video games using Neuralink's device.