Analog Circuit Design Cadence

Nvited Paper

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically con- stitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the in- creasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the mo- tivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, sym- bolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

Keywords—Analog and mixed-signal computer-aided design (CAD), analog and mixed-signal integrated circuits, analog circuit and layout synthesis, analog design automation, circuit simulation and modeling.

Ntroduction

The microelectronics market and, in particular, the mar- kets for application-specific ICs (ASICs), application-spe- cific standard parts (ASSPs), and high-volume commodity ICs are characterized by an ever-increasing level of integra- tion complexity, now featuring multimillion transistor ICs.

In recent years, complete systems that previously occupied one or more boards have been integrated on a few chips or even one single chip. Examples of such systems on a chip (SoC) are the single-chip TV or the single-chip camera or new generations of integrated telecommunication systems that include analog, digital, and eventually radio-frequency (RF) sections on one chip. The technology of choice for Universiteit Leuven, Leuven, Belgium.

R. A. Rutenbar is with the Electrical and Computer Engineering Depart- Publisher Item Identifier S 0018-9219(00)10757-1. these systems is of course CMOS, because of the good dig- ital scaling, but also BiCMOS is used when needed for the analog or RF circuits. Although most functions in such inte- grated systems are implemented with digital or digital signal processing (DSP) circuitry, the analog circuits needed at the interface between the electronic system and the “real” world are also being integrated on the same die for reasons of cost and performance. A typical future SoC might look like Fig. 1, containing several embedded processors, several chunks of embedded memory, some reconfigurable logic, and a few analog interface circuits to communicate with the continuous-valued external world.

Despite the trend previously to replace analog circuit functions with digital computations (e.g., digital signal processing in place of analog filtering), there are some typical functions that will always remain analog.

• The first typically analog function is on the input side of a system: signals from a sensor, microphone, an- tenna, wireline, and the like, must be sensed or re- ceived and then amplified and filtered up to a level that allows digitization with sufficient signal-to-noise-and- distortion ratio. Typical analog circuits used here are low-noise amplifiers, variable-gain amplifiers, filters, oscillators, and mixers (in case of downconversion).

Applications are, for instance, instrumentation (e.g., data and biomedical), sensor interfaces (e.g., airbag ac- celerometers), process control loops, telecommunica- tion receivers (e.g., telephone or cable modems, wire- less phones, set-top boxes, etc.), recording (e.g., speech recognition, cameras), and smart cards.

• The second typically analog function is on the output side of a system: the signal is reconverted from dig- ital to analog form and it has to be strengthened so that it can drive the outside load (e.g., actuator, an- tenna, loudspeaker, wireline) without too much distor- tion. Typical analog circuits used here are drivers and buffers, filters, oscillators and mixers (in case of upcon- version). Applications are, for instance, process control Fig. 1.

Future system-on-a-chip. loops (e.g., voltage regulators for engines), telecommu- nication transmitters, audio and video (e.g., CD, DVD, loudspeakers, TV, PC monitors, etc.), and biomedical actuation (e.g., hearing aids).

• The third type of blocks are the true mixed-signal circuits that interface the above analog circuits with

Here Are The Sample-And-Hold Circuits For Signal

sampling, analog-to-digital converters for amplitude discretization, digital-to-analog converters for signal reconstruction, and phase-locked loops and frequency synthesizers to generate a timing reference or perform timing synchronization.

• In addition, the above circuits need stable absolute references for their operation, which are generated by voltage and current reference circuits, crystal oscilla- tors, etc.

• Finally, the largest analog circuits today are high- performance (high-speed, low-power) digital circuits. Typical examples are state-of-the-art microprocessors, which are largely custom sized like analog circuits, to push speed or power limits.

Clearly, analog circuits are indispensable in all electronic applications that interface with the outside world and will even be more prevalent in our lives if we move toward the intelligent homes, the mobile road/air offices, and the wire- less workplaces of the future.

When both analog (possibly RF) and digital circuits are needed in a system, it becomes obvious to integrate them together to reduce cost and improve performance, provided the technology allows us to do so. The growing market share of integrated mixed-signal ICs observed today in modern electronic systems for telecommunications, consumer, com- puting, and automotive applications, among many others, is a direct result of the need for higher levels of integration . Since the early 1990s, the average growth rate of the mixed-signal IC market has been between 15% and 20% per year, and this market is predicted to surpass $22 billion by 2001. Recent developments in CMOS technology have offered the possibility to combine good and scalable digital performance with adequate analog performance on the same die. The shrinking of CMOS device sizes down to the deep submicrometer regime (essentially in line with, or even ahead of, the predicted technology roadmap ) makes higher levels of system integration possible and also offers analog MOS transistor performance that approaches the performance of a bipolar transistor. This explains why CMOS is the technology of choice today, and why other technologies like BiCMOS are only used when more ag- gressive bipolar device characteristics (e.g., power, noise, or distortion) are really needed. The technology shift from bipolar to CMOS (or BiCMOS) has been apparent in most applications. Even fields like RF, where traditionally GaAs and bipolar were the dominant technologies, now show a trend toward BiCMOS (preferably with a SiGe option) and even plain CMOS for reasons of higher integration and cost reduction. These higher levels of mixed-signal integration, however, also introduce a whole new set of problems and design effects that need to be accounted for in the design process.

Indeed, together with the increase in circuit com- plexity, the design complexity of today’s ICs has increased drastically: 1) due to integration, more and more transis- tors are combined per IC, performing both analog and digital functions, to be codesigned together with the em- bedded software; 2) new signal processing algorithms and corresponding system architectures are developed to accommodate new required functionalities and performance requirements (including power) of emerging applications; and 3) due to the rapid evolution of process technologies, the expectation for changing process technology parameters needs to be accounted for in the design cycle. At the same time, many ASIC and ASSP application markets are char- acterized by shortening product life cycles and tightening time-to-market constraints. The time-to-market factor is very critical for ASICs and ASSPs that eventually end up in consumer, telecom, or computer products: if one misses the initial market window relative to the competition, prices and, therefore, profit can be seriously eroded.

The key to managing this increased design complexity while meeting the shortening time-to-market factor is the use of computer-aided design (CAD) and verification tools. Today’s high-speed workstations provide ample power to make large and detailed computations possible.

What is needed to expedite the analog and mixed-signal design process is a structured methodology and supporting CAD tools to manage the entire design process and design complexity. CAD tools are also needed to assist or automate many of the routine and repetitive design tasks, taking away the tedium of manually designing these sections and pro- viding the designer with more time to focus on the creative aspects of design. ICs typically are composed of many identical circuit blocks used across different designs. The design of these repetitive blocks can be automated to reduce the design time. In addition, CAD tools can increase the pro- ductivity of designers, even for nonrepetitive analog blocks.

Therefore, analog CAD and circuit design automation are likely to play a key role in the design process of the next generation of mixed-signal ICs and ASICs. And although the design of mixed-signal ASICs served as the initial impetus for stepping up the efforts in research and development of analog design automation tools, the technology trend toward integrating complete systems on a chip in recent years has provided yet another driving force to bolster analog CAD efforts. In addition, for such systems new design paradigms are being developed that greatly affect how we will design analog blocks. One example is the macrocell design reuse methodology of assembling a system by reusing soft or hard macrocells (“virtual components”) that are available on the intellectual property (IP) market and that can easily be mixed and matched in the “silicon board” system if they comply with the virtual socket inferface (VSI) standard . This methodology again poses many new constraints, also on the analog blocks. Platform-based design is another emerging system-level design methodology .

In the digital domain, CAD tools are fairly well developed and commercially available today, certainly for the lower levels of the design flow. First, the digital IC market is much larger than the analog IC market. In addition, unlike analog circuits, a digital system can naturally be represented in terms of Boolean representation and programming language con- structs, and its functionality can easily be represented in al- gorithmic form, thus paving the way for a logical transi- tion into automation of many aspects of digital system de- sign. At the present time, many lower-level aspects of the digital design process are fully automated. The hardware is described in a hardware description language (HDL) such as VHDL or Verilog, either at the behavioral level or most often at the structural level. High-level synthesis tools at- tempt to synthesize the behavioral HDL description into a structural representation. Logic synthesis tools then translate the structural HDL specification into a gate-level netlist, and semicustom layout tools (place and route) map this netlist into a correct-by-construction mask-level layout based on a cell library specific for the selected technology process. Re- search interest is now moving in the direction of system syn- thesis where a system-level specification is translated into a hardware–software coarchitecture with high-level specifica- tions for the hardware, the software, and the interfaces. Reuse methodologies and platform-based design methodologies are being developed to further reduce the design effort for com- the push-button stage, but the developments are keeping up reasonably well with the chip complexity offered by the tech- nology.

Unfortunately, the story is quite different on the analog side. There are not yet any robust commercial CAD tools to support or automate analog circuit design apart from circuit simulators (in most cases, some flavor of the ubiquitous SPICE simulator ) and layout editing environments and their accompanying tools (e.g., some limited optimization capabilitiesaroundthesimulator,orlayoutverificationtools).

Some of the main reasons for this lack of automation are that analog design in general is perceived as less systematic and more heuristic and knowledge-intensive in nature than digital design, and that it has not yet been possible for analog designers to establish a higher level of abstraction that shields all the device-level and process-level details from the higher level design. Analog IC design is a complex endeavor, requiring specialized knowledge and circuit design skills acquired through many years of experience. The variety of circuitschematicsandthenumberofconflictingrequirements and corresponding diversity of device sizes is also much larger. In addition, analog circuits are more sensitive to nonidealitiesandallkindsofhigherordereffectsandparasitic disturbances (crosstalk, substrate noise, supply noise, etc.).

Thesedifferencesfromdigitaldesignalsoexplainwhyanalog CAD tools cannot simply adapt the digital algorithms, but why specific analog solutions need to be developed that are targeted to the analog design paradigm and complexity.

The analog CAD field, therefore, had to evolve on its own, but it turned into a niche field as the analog IC market was smaller than the digital one. As a result, due to the lack of adequate and mature commercial analog CAD tools, analog designs today are still largely being handcrafted with only a SPICE-like simulation shell and an interactive layout environment as supporting facilities. The design cycle for analog and mixed-signal ICs remains long and error-prone. Therefore, although analog circuits typically occupy only a small fraction of the total area of mixed-signal ICs, their design is often the bottleneck in mixed-signal systems, both in design time and effort as well as test cost, and they are often responsible for design errors and expensive reruns.

The Economic Pressure For High-Quality Yet Cheap

electronic products and the decreasing time-to-market constraints have clearly revealed the need in the present microelectronics industry for analog CAD tools to assist designers with fast and first-time-correct design of analog circuits, or even to automate certain tasks of this design process where possible. The push for more and more inte- grated systems containing both analog and digital circuitry heavily constrains analog designers. To keep pace with the digital world and to fully exploit the potential offered by the present deep submicrometer VLSI technologies, boosting analog design productivity is a major concern in the industry today. The design time and cost for analog circuits from specification to successful silicon has to be reduced drastically. The risk for design errors impeding first-pass functional (and possibly also parametrically correct) chips has to be eliminated. Second, analog CAD tools can also help to increase the quality of the resulting designs. Before starting detailed circuit implementation, more higher-level explorations and optimizations should be performed at the system architectural level, preferrably across the analog–digital boundary, since decisions at those levels have a much larger impact on key overall system parameters such as power consumption and chip area.

Likewise, designs at lower levels should be “automated” where possible. Designers find difficulty in considering multiple conflicting tradeoffs at the same time—computers do not. Computers are adept at trying out and exploring large numbers of competing alternatives. Typical examples are fine-tuning through optimization of an initial hand- crafted design and improving design robustness with respect to operating parameter variations (temperature, supply voltage) and/or with respect to manufacturing tolerances and GIELEN AND RUTENBAR: COMPUTER-AIDED DESIGN OF ANALOG AND MIXED-SIGNAL INTEGRATED CIRCUITS Fig. 2.

SIA synthesis potential solutions roadmap . mismatches. Third, the continuous pressure of technology updates and process migrations is a large burden on analog designers. CAD tools could take over a large part of the technology retargeting effort, and could make analog design easier to port or migrate to new technologies. Finally, the SoC design reuse methodology also requires executable models and other information for the analog macrocells to be used in system-level design and verification. Tools and modeling techniques have to be developed to make this possible. This need for analog CAD tools beyond simulation has also clearly been identified in the SIA roadmap, as indicated in Fig. 2, where analog synthesis is predicted to take off somewhere beyond the year 2000 .

Despite the lack of commercial analog CAD tools, analog CAD and design automation over the past 15 years has been a field of profound academic and industrial research activity, although with not quite as many researchers as in the digital world, resulting in a slow but steady progress . Some of the aspects of the analog CAD field are fairly mature, some are ready for commercialization, while others are still in the process of exploration and development.

The simulation area has been particularly well developed since the advent of the SPICE simulator, which has led to the development of many simulators, including timing simulators in the digital field and the newer generation of mixed-signal and multilevel commercial simulators. Analog circuit and layout synthesis has recently shown promising results at the research level, but commercial solutions are only starting to appear in the marketplace. The development of analog and mixed-signal hardware description languages

Like Vhdl-Ams And Verilog-A/Ms Is Intended To

provide a unifying trend that will link the various analog designautomationtasksinacoherentframeworkthatsupports a more structured analog design methodology from the design conceptualization stage to the manufacturing stage.

They also provide a link between the analog and the digital domains, as needed in designing mixed analog–digital ICs and the SoC of the future.

In this survey, the relevant developments to date in analog and mixed-signal CAD will be covered in a general overview. The paper is organized as follows. Section II describes the analog and mixed-signal integrated system design process, as well as a hierarchical design strategy for the analog blocks.

Section III then describes general progress and the current status in the various fields of analog CAD: simulation and modeling, symbolic analysis, circuit synthesis and optimiza- tion, layout generation, yield analysis and design centering, and test and design for testability. This is illustrated with sev- eral examples. Most of the emphasis will be on circuit and layout synthesis as it is key to analog design automation, while other topics such as test will only be covered briefly in this paper. For the sake of completeness, we did not want to omit those topics, but they require overview papers of their own for detailed coverage. Conclusions are then provided in Section IV, and an extensive list of references completes the paper.

Analog And Mixed-Signal Design Process

We will now first describe the design flow for mixed-signal integrated systems from concept to chip, followed by the de- scription of a hierarchical design methodology for the analog

A. Mixed-Signal Ic Design Flow

Fig. 3 illustrates a possible scenario for the design flow of a complex analog or mixed-signal IC. The various stages that are traversed in the design process are as follows.

1) Conceptual Design: This is typically the product con- ceptualization stage, where the specifications for a design Fig. 3.

High-level view of the analog or mixed-signal IC design process. are gathered and the overall product concept is developed. Careful checking of the specifications is crucial for the later success of the product in its application context. Mathemat- ical tools such as Matlab/Simulink are often used at this stage. This stage also includes setting project management goals such as final product cost and time-to-market, project planning, and tracking.

2) System Design: This is the first stage of the actual design, where the overall architecture of the system is de- signed and partitioned. Hardware and software parts are de- fined and both are specified in appropriate languages. The hardware components are described at the behavioral level, and, in addition, the interfaces have to be specified. This stage includes decisions about implementation issues, such as package selection, choice of the target technology, and general test strategy. The system-level partitioning and spec- ifications are then verified using detailed cosimulation tech- niques.

3) Architectural Design: This stage is the high-level decomposition of the hardware part into an architecture consisting of functional blocks required to realize the spec- ified behavioral description. This includes the partitioning between analog and digital blocks. The specifications of the various blocks that compose the design are defined, and all blocks are described in an appropriate hardware description language (e.g., VHDL and VHDL-AMS). The high-level architecture is then verified against the specifications using behavioral mixed-mode simulations.

4) Cell Design: For the analog blocks, this is the detailed implementation of the different blocks for the given specifi- cations and in the selected technology process, resulting in a fully sized device-level circuit schematic. The stage encom- passes both a selection of the proper circuit topology and a dedicated sizing of the circuit parameters. Throughout this process, more complex analog blocks will be further decom- posed into a set of subblocks. This whole process will be described in more detail in Section II-B. Manufacturability considerations (tolerances and mismatches) are taken into ac- count in order to guarantee a high yield and/or robustness.

The resulting circuit design is then verified against the spec- ifications using SPICE-type circuit simulations. 5) Cell Layout: This stage is the translation of the elec- trical schematic of the different analog blocks into a geomet- rical representation in the form of a multilayer layout. This stage involves area optimization to generate layouts that oc- cupy a minimum amount of chip real-estate. The layout is followed by extraction of layout parasitics and detailed cir- cuit-level simulations of the extracted circuit in order to en- sure that the performance characteristics do not deviate on account of layout parasitics.

6) System Layout: The generation of the system-level layout of an IC not only includes system-level block place and route, but also power-grid routing. Crosstalk and sub- strate coupling analysis are important in mixed-signal ICs, and proper measures such as shielding or guarding must also be included. Also, the proper test structures are inserted to make the IC testable. Interconnect parasitics are extracted and detailed verification (e.g., timing analysis) is performed.

Finally, the system is verified by cosimulating the hardware part with the embedded software. GIELEN AND RUTENBAR: COMPUTER-AIDED DESIGN OF ANALOG AND MIXED-SIGNAL INTEGRATED CIRCUITS 7) Fabrication and Testing: This is the processing stage where the masks are generated and the ICs fabricated. Testing is performed during and after fabrication in order to reject defective devices.

Note that any of the many simulation and verification stages throughout this design cycle may detect potential problems with the design failing to meet the target require- ments. In that case, backtracking or redesign will be needed, as indicated by the upward arrow on the left-hand side of Fig. 3.

B. Hierarchical Analog Design Methodology

This section focuses on the design methodology adopted for the design of analog integrated circuits. These analog cir- cuits could be part of a larger mixed-signal IC. Although at the present time there is no clear-cut general design method- ology for analog circuits yet, we outline here the hierarchical design methodology prevalent in many of the emerging ex- perimental analog CAD systems –. For the design of a complex analog macroblock such as a phase-locked loop or an analog-to-digital converter, the analog block is typi- cally decomposed into smaller subblocks (e.g., a comparator or a filter). The specifications of these subblocks are then derived from the initial specifications of the original block, after which each of the subblocks can be designed on its own, possibly by further decomposing it into even smaller sub- blocks. In this way, constraints are passed down the hierarchy in order to make sure that the top-level block in the end meets the specifications. This whole process is repeated down the decomposition hierarchy until a level is reached that allows a physical implementation (either the transistor level or a higher level in case analog standard cells or IP macrocells are used). The top–down synthesis process is then followed by a bottom–up layout implementation and design verification process. The need for detailed design verification is essential since manufacturing an IC is expensive, and a design needs to be ensured to be fully functional and meet all the design requirements within a window of manufacturing tolerances, before starting the actual fabrication. When the design fails to meet the specifications at some point in the design flow, redesign iterations are needed.

Most experimental analog CAD systems today use a per- formance-driven design strategy within such analog de- sign hierarchy. This strategy consists of the alternation of

A) Layout Generation;

b) detailed design verification (after extraction). Topology selection is the step of selecting the most appro- priate circuit topology that can best meet the given specifi- cations out of a set of already known alternative topologies.

Fig. 4. Hierarchical design strategy for analog circuits. (An alternative is that the designer develops his/her own new topology.) A topology can be defined hierarchically in terms of lower-level subblocks. For an analog-to-digital converter, for instance, topology selection could be selecting between

Or Any Other

topology that can best realize the specifications. Specification translation is then the step of mapping the specifications for the block under design at a given level (e.g., a converter) into individual specifications for each of the subblocks (e.g., a comparator) within the selected block topology, so that the complete block meets its specifica- tions, while possibly optimizing the design toward some application-specific design objectives (e.g., minimal power consumption). The translated specifications are then verified by means of (behavioral or circuit) simulations before proceeding down in the hierarchy. Behavioral simulations are needed at higher levels in the design hierarchy (when no device-level implementation is available yet); circuit simulations are used at the lowest level in the design hier- archy. At this lowest level, the subblocks are single devices and specification translation reduces to circuit sizing (also called circuit dimensioning), which is the determination of all device sizes, element values, and bias parameters in the circuit tuned to the given specifications.

Layout generation is the step of generating the geomet- rical layout of the block under design, by assembling (place and route) the already generated layouts of the composing subblocks. At the lowest level, these subblocks are individual devices or selected device groupings, which themselves are generated by parameterized procedural device layout gener- ators. Also, power, ground, and substrate connection routing is part of the layout generation step. This step is followed by extraction and, again, detailed verification and simulation to check the impact of the layout parasitics on the overall cir- cuit performance.

The above methodology is called performance-driven or constraint-driven, as the performance specifications are the driving input to each of the steps: each step tries to per- form its action (e.g., circuit sizing or layout generation) such that the input constraints are satisfied. This also implies that throughout the design flow, constraints need to be propa- gated down the hierarchy in order to maintain consistency in the design as it evolves through the various design stages and to make sure that the top-level block in the end meets its target specifications. These propagated constraints may include performance constraints, but also geometrical con- straints (for the layout), or manufacturability constraints (for yield), or even test constraints. Design constraint propagation is essential to ensure that specifications are met at each stage of the design, which would also reduce the number of re- design iterations. This is the ultimate advantage of top–down design: catch problems early in the design flow and, there- fore, have a higher chance of first-time success, while ob- taining a better overall system design.

Ideally, one would like to have one clean top–down de- sign path. However, this rarely occurs in practice, as a re- alistic design needs to account for a number of sometimes hard-to-quantify second-order effects as the design evolves.

For instance, a choice of a particular topology for a function block may fail to achieve the required specifications or per- formance specifications may be too tight to achieve, in which case a redesign step is necessary to alter the block topology or loosen the design specifications. In the above top–down/ bottom–up design flow, redesign or backtracking itera- tions may therefore be needed at any point where a design step fails to meet its input specifications. In that case, one or more of the previously executed steps will have to be redone, for example, another circuit topology can be selected instead of the failing one, or another partitioning of subblock spec- ifications can be performed. One of the big differences be- tween analog or mixed-signal designs and the more straight top–down digital designs is exactly the larger number of de- sign iterations needed to come to a good design solution. The adoption of a top–down design methodology is precisely in- tended to reduce this disadvantage.

A question that can be posed is why the analog circuits need to be redesigned or customized for every new applica- tion. The use of a library of carefully selected analog standard cells can be advantageous for certain applications, but is in general inefficient and insufficient. Due to the large variety and range of circuit specifications for different applications, any library will only have a partial coverage for each appli- cation, or it will result in an excess power and/or area con- sumption that may not be acceptable for given applications.

Many high-performance applications require an optimal de- sign solution for the analog circuits in terms of power, area, and overall performance. A library-based approach would require an uneconomically large collection of infrequently used cells. Instead, analog circuits are better custom tailored toward each specific application and tools should be avail- able to support this. In addition, the porting of the library cells whenever the process changes is a serious effort, that would also require a set of tools to automate.

The following section in this survey paper will describe the progress and the current state of the art in CAD tool devel- opment for the main tasks needed in the above analog design methodology: simulation and modeling, symbolic analysis, circuit synthesis, layout generation, yield estimation and de- sign centering, test, and design for testability.

Esign Automation

A. Numerical Simulation of Analog and Mixed-Signal

Ircuits

A key to ensuring design correctness is the use of simula- tion tools. Simulation tools have long been in use in the IC design process and provide a quick and cost-effective means of design verification without actual fabrication of the de- vice. The most widely used analog CAD tool today, there- fore, is a circuit simulator that numerically calculates the re- sponse of the circuit to an input stimulus in the time or fre- quency domain. In the design methodology of Fig. 4, sim- ulation plays a key role. First of all—and this has been its traditional role—simulation is critical for detailed verifica- tion after a design has been completed (before layout as well as after extraction from the layout). Analog integrated cir- cuits are typically impacted by many higher order effects that can severely degrade the circuit performance once fabri- cated, if the effects are not properly accounted for during the design process. Circuit simulation is a good design aid here by providing the capability of simulating many of the higher order effects and verifying circuit performance prior to fab- rication, provided the effects are modeled properly. Second, a result of adopting the top–down design paradigm, simula- tion is needed to explore tradeoffs and verify designs at a high level, before proceeding with the detailed implementation of the lower-level subblocks. The latter also implies a higher level of modeling for the analog blocks. Finally, executable simulation models are also part of the interface needed to enable the integration of complex systems on a chip by com- bining IP macrocells.

1) Circuit Simulation: Circuit simulation began with the

, Which Spawned Many Of The Cad And Ic Design Ef-

forts and has been the cornerstone of many of today’s IC de- signs. The SPICE simulator is to an analog designer what a calculator is to an engineering school sophomore. Advances in mathematics and the development of many new and effi- cient numerical algorithms as well as advances in interfaces (e.g., user interfaces, waveform displays, script languages, etc.) have over the years contributed to a vast number of com- mercial CAD tools. Many variants of the SPICE simulator are now marketed by a number of CAD vendors; many of the IC manufacturers have in-house versions of the SPICE sim- ulator that have been adapted to their own proprietary pro- cesses and designs. These simulators have been fine-tuned to GIELEN AND RUTENBAR: COMPUTER-AIDED DESIGN OF ANALOG AND MIXED-SIGNAL INTEGRATED CIRCUITS

Ifferent Analog Hardware Description Levels

meet the convergence criteria of the many difficult-to-sim- ulate ICs. SPICE or its many derivatives have evolved into an established designer utility that is being used both during the design phase (often in a designer-guided trial-and-error fashion) and for extensive postlayout design verification.

A problem that has frustrated analog designers for many years is the limited accuracy of the semiconductor device models used in these simulators, especially for small-signal parameters and on the boundary between different operating regions of the devices (where the earlier models had dis- continuities). Fortunately, recent models such as BSIM3 v3, Philips model 9 or EKV look more promising for analog design by providing smooth and continuous transitions be- tween different operating regions . For RF applications, however, even these models are not accurate enough, and the latest research work concentrates on analyzing and modeling the extra effects that become important at higher operating frequencies (e.g., the distributed gate, the resistive bulk, and nonquasi-static effects) .

With the explosion of mixed-signal designs, the need has also arisen for simulation tools that allow not only simu- lation of analog or digital circuits separately, but also sim- ulation of truly mixed analog–digital designs . Simu- lating the large digital parts with full SPICE accuracy re- sults in very long overall simulation times, whereas efficient event-driven techniques exist to simulate digital circuits at higher abstraction levels than the transistor level. Therefore, mixed-mode simulators were developed that glue together an accurate SPICE-like analog simulator to an efficient digital simulator. These so-called glued mixed-mode simulators address the conversions of the signals between analog and digital signal representations and of the appropriate loading effects by inserting interface elements at the boundaries be- tween analog and digital circuitry. Also, the synchronization between the analog kernel with its tiny integration steps and the digital kernel with its events determines the efficiency of the overall simulation. Such synchronization is needed at each time point when an event crosses the boundary between analog or digital. Today, the trend clearly is toward a more unified level of algorithm integration with single-kernel mul- tiple-solver solutions, and commercial solutions following that line have recently appeared in the marketplace.

2) Circuit Modeling: In recent years, the need has also arisen for higher levels of abstraction to describe and simulate analog circuits. There are three reasons for this.

In a top–down design methodology at higher levels of the design hierarchy, where the detailed lower-level circuit implementations are yet unknown, there is a need for higher-level models describing the pin-to-pin behavior of the circuits rather than the (yet unknown) internal structural implementation. Second, the verification of integrated mixed-signal systems also requires higher description levels for the analog sections, since such integrated systems are computationally too complex to allow a full simulation of when providing or using analog IP macrocells in a SoC context, the virtual component has to be accompanied by an executable model that efficiently models the pin-to-pin behavior of the virtual component. This model can then be used in system-level design and verification, even without knowing the detailed circuit implementation of the macro- cell.

To solve those three problems, modeling paradigms and languages from the digital world have migrated to the analog domain. For this reason, macro, behavioral, and functional simulation levels have been developed for analog circuits be- sides the well-known circuit level . For a commercial simulator to be useful in current industrial mixed-signal de- sign practice, it therefore has to be capable of simulating a system containing a mix of analog blocks described at dif- ferent levels and in different domains, in combination with digital blocks. This requires a true mixed-signal, multilevel, mixed-domain simulator.

Table 1 gives an overview of the different analog de- scription levels, both for continuous-time and discrete-time analog circuits . In a macromodel, an equivalent but computationally cheaper circuit representation is used that has approximately the same behavior as the original circuit. Equivalent sources combine the effect of several other elements that are eliminated from the netlist. The simulation speed-up is roughly proportional to the number of nonlinear devices that can be eliminated. In a behavioral or functional model, a purely mathematical description of the input–output behavior of the block is used. This typically will be in the form of a set of differential-alge- braic equations (DAE) and/or transfer functions. At the behavioral level, conservation laws still have to be satisfied on the pins connecting different blocks. At the functional level, this is no longer the case and the simulated system turns into a kind of signal-flow diagram. Fig. 5 shows an example of the output response of a CMOS current-steering digital-to-analog converter, modeled at the full device level Fig. 5(b) and at the behavioral level Fig. 5(a). The responses are quite similar (the error between the two time-domain responses for the same input signal is less than 1%), while the behavioral model simulates about 1000 times faster.

To allow an easy exchange of these models across dif- ferent simulators and different users, the need arose for standardized analog hardware description languages in which to describe these higher-level models. These language standards have to provide a consistent way of representing and sharing design information across the different design tasks and across the design hierarchy, and, therefore, provide a unifying trend to link the various tools in a global analog CAD system. For mixed-signal designs, the analog HDLs had to be compatible with the existing digital HDLs (such as VHDL and Verilog). Several parallel analog or mixed-signal HDL language standardization efforts, therefore, have been initiated, recently resulting in the standardized languages

Hdl-Ams And Verilog-A/Ms . The Vhdl-Ams

language targets the mixed-signal domain and is a superset of the digital VHDL language. Verilog-A for the analog part and Verilog-MS for the mixed-signal part target com- patibility with the Verilog language. Recently, also, the standardization of an extension of VDHL-AMS toward RF has been started.

One of the remaining difficulties with higher-level analog modeling is the automatic characterization of analog circuits and more particularly the automatic generation of analog macromodels or behavioral models from a given design.

This is a difficult problem area that needs to be addressed in the near future, as it might turn out to be the biggest hurdle for the adoption of these high-level modeling methodologies and AHDLs in industrial design practice. Current approaches can roughly be divided into fitting approaches and construc- tive approaches. In the fitting approaches, a parameterized model (for example, a rational transfer function, a more gen- eral set of equations, or even a neural network model) is first proposed by the model developer and the values of the pa- rameters are then fitted by some least-square error optimiza- tion so that the model response matches as closely as pos- sible the response of the real circuit –. The problem with this approach is that first a good model template must be proposed. The second class of methods, therefore, tries to generate or build a model from the underlying circuit de- scription. One approach, for instance, uses symbolic simpli-

(B)

Fig. 5. Comparison of the output response to the same input waveform of a digital-to-analog converter modeled at the behavioral level (a) and at the circuit level (b). The horizontal axis is time in seconds.

fication techniques to simplify the physical equations that de- scribe the circuit up to a maximum error bound . Up until now, however, the gains in CPU time were not high enough for practical circuits. More research in this area is definitely needed.

3) Dedicated Simulation Techniques: In addition to the above general-purpose simulation tools for analog and mixed-signal circuits, other techniques or tools have been developed for dedicated purposes. An important class of circuits that are used in many signal processing and communication systems are the switched circuits, like switched-capacitor and, more recently, switched-current circuits. Their switched nature, with the resulting switching transients, requires many small numerical integration steps to be simulated within each clock phase if a standard SPICE simulator is used. On the other hand, advantage can be taken of the periodically switched nature of the circuits and the fact that in a time-discrete circuit the signals are only important and, thus, only have to be calculated at specific time points (e.g., the end of each clock phase). This is exploited in several switched-capacitor simulation tools like

Switcap , And Swap But Also In Dedicated

tools like TOSCA that analyzes switched-capacitor-based converters . Another important domain is RF simulation, needed for instance when developing circuits for wireless applications, where modulated signals have to be simulated and effects like noise, distortion, and intermodulation become impor- GIELEN AND RUTENBAR: COMPUTER-AIDED DESIGN OF ANALOG AND MIXED-SIGNAL INTEGRATED CIRCUITS tant. Here, techniques have been developed to directly simu- late the steady-state behavior of these circuits without having to wait for the decay of the initial transients , . In the time domain, shooting methods are used for this, which tend to be more suited for strongly nonlinear circuits. In the fre- quency domain, harmonic balance methods are used, which allow a simulation of the steady-state behavior of nonlinear circuits driven by one- or two-tone signals but which histor- ically required large CPU times and memory sizes for large circuits or for strong nonlinearities. Recently, the implicit matrix technique in combination with both shooting or har- monic balance methods extended the range of these methods to much larger circuits . In parallel, other techniques have been developed such as the envelope simulation technique , which combines time and frequency domain simulation to efficiently calculate the circuit’s response to truly modu- lated signals by separating the carrier from the modulation signal. Other dedicated simulation algorithms have been de- veloped for specific applications such as the high-level anal- ysis of entire analog RF receiver front ends in the ORCA tool , or for the analysis of nonlinear noise and phase noise in both autonomous and driven circuits such as oscillators, mixers, and frequency synthesizers , .

An Important Problem In Deep Submicrometer Tech-

nologies where interconnect delays are exceeding gate delays is the analysis of interconnect networks during postlayout timing verification. Accurate models for each wire segment and the driving gates are needed, which makes the overall interconnect network too complex to simulate. Therefore, recent developments try to improve the efficiency of timing verification while keeping the accuracy by using piecewise-linear models for gates and model-order reduction techniques for the interconnect network . The complexity of the interconnect network can be reduced by techniques such as asymptotic waveform evaluation (AWE) or related variants such as Padé via Lanczos (PVL), that use moment matching and Padé approximation to generate a lower order model for the response of a large linear circuit like an interconnect network. The early AWE efforts used explicit moment matching techniques, which could generate unstable reduced-order models. Subsequent developments using iterative methods resulted in methods like PVL that overcome many of the deficiencies of the earlier AWE efforts, and stability is now guaranteed using techniques like Arnoldi transformations . The interconnect delay problem has become so important that it is now driving the layout generation to get in-time timing closure, and that it even is becoming essential for synthesis (where, of course, estimation techniques must be used) .

An important problem in mixed-signal ICs is signal in- tegrity analysis: the analysis of crosstalk and couplings such as capacitive or inductive interconnect couplings or cou- plings through the supply lines or the substrate. Crosstalk can be a limiting factor in today’s high-speed circuits with many layers of interconnect. Substrate or supply coupling noise is particularly important for analog circuits, especially where they have to sense small input signals, such as in re- ceiver front ends. Research has been going on to find efficient yet accurate techniques to analyze these problems, which de- pend on the geometrical configuration and, therefore, are in finite difference methods or boundary element methods are used to solve for the substrate potential distribution due to in- jected noise sources –. Recently, these methods have been speeded up with similar acceleration techniques as in RF or interconnect simulation, e.g., using an eigendecompo- sition technique . Their efficiency even allows one to per- form some substrate design optimizations . A problem is that the noise-generating sources (i.e., the switching noise injected by the digital circuitry) are not accurately known, but vary with time depending on the input signals or the em- bedded programs, and, therefore, have to be estimated sta- tistically. Some attempts to solve this problem characterize every cell in a digital standard cell library by the current they inject in the substrate due to an input transition, and then cal- culate the total injection of a complex system by summing the contributions of all switching cells over time .

B. Symbolic Analysis Of Analog Circuits

Analog design is a very complex and knowledge-inten- sive process, which heavily relies on circuit understanding and related design heuristics. Symbolic circuit analysis tech- niques have been developed to help designers gain a better understanding of a circuit’s behavior. A symbolic simulator is a computer tool that takes as input an ordinary (SPICE- type) netlist and returns as output (simplified) analytic ex- pressions for the requested circuit network functions in terms of the symbolic representations of the frequency variable and (some or all of) the circuit elements , . They perform the same function that designers traditionally do by hand analysis (even the simplification). The difference is that the analysis is now done by the computer, which is much faster, can handle more complex circuits, and does not make as many errors. An example of a complicated BiCMOS opamp is shown in Fig. 6. The (simplified) analytic expression for the differential small-signal gain of this opamp has been an-

Alyzed With The Symba Tool And Is Shown Below

The symbolic expression gives a better insight into which small-signal circuit parameters predominantly determine the gain in this opamp and how the user has to design the circuit to meet a certain gain constraint. In this way, symbolic circuit analysis is complementary to numerical (SPICE) circuit sim- ulation, which was described in the previous section. Sym- bolic analysis provides a different perspective that is more suited for obtaining insight in a circuit’s behavior and for cir- cuit explorations, whereas numerical simulation is more ap- propriate for detailed design validation once a design point has been decided upon. In addition, the generated symbolic Fig. 6.

BiCMOS operational amplifier to illustrate symbolic analysis. design equations also constitute a model of the circuit’s be- havior that can be used in CAD tasks such as analog syn- thesis, statistical analysis, behavioral model generation, or formal verification .

At this moment, only symbolic analysis of linear or small- signal linearized circuits in the frequency domain is pos- sible, both for continuous-time and discrete-time (switched) analog circuits , , . In this way, symbolic expres- sions can be generated for transfer functions, impedances, noise functions, etc. In addition to understanding the first- order functional behavior of an analog circuit, a good under- standing of the second-order effects in a circuit is equally im- portant for the correct functioning of the design in its system application later on. Typical examples are the PSRR and the CMRR of a circuit, which are limited by the mismatches be- tween circuit elements. These mismatches are represented symbolically in the formulas. Another example is the distor- tion or intermodulation behavior, which is critical in telecom applications. The technique of symbolic simulation has been extended to the symbolic analysis of distortion and intermod- ulation in weakly nonlinear analog circuits where the nonlin- earity coefficients of the device small-signal elements appear in the expressions .

Exact symbolic solutions for network functions, however, are too complex for linear(ized) circuits of practical size, and even impossible to calculate for many nonlinear effects. Even rather small circuits lead to an astronomically high number of terms in the expressions, that can neither be handled by the computer nor interpreted by the circuit designer. There- fore, since the late 1980s, and in principle similar to what designers do during hand calculations, dedicated symbolic analysis tools have been developed that use heuristic sim- plification and pruning algorithms based on the relative im- portance of the different circuit elements to reduce the com- plexity of the resulting expressions and retain only the dom- inant contributions within user-controlled error tolerances.

Examples Of Such Tools Are Isaac , Synap , And

ASAP among many others. Although successful for rel- atively small circuits, the fast increase of the CPU time with the circuit size restricted their applicability to circuits be- tween 10 and 15 transistors only, which was too small for many practical applications.

In recent years, however, an algorithmic breakthrough in the field of symbolic circuit analysis has been realized. The techniques of simplification before and during the symbolic expression generation, as implemented in tools like SYMBA

And Rainier , Highly Reduce The Computation Time

and, therefore, enable the symbolic analysis of large analog circuits of practical size (like the entire 741 opamp or the ex- ample of Fig. 6). In simplification before generation (SBG), the circuit schematic, or some associated matrix or graph(s), are simplified before the symbolic analysis starts , .

In simplification during generation (SDG), instead of gen- erating the exact symbolic expression followed by pruning the unimportant contributions, the desired simplified expres- sion is built up directly by generating the contributing domi- nant terms one by one in decreasing order of magnitude, until the expression has been generated with the desired accuracy , .

All these techniques, however, still result in large, ex- panded expressions, which restricts their usefulness for larger circuits. Therefore, for really large circuits, the technique of hierarchical decomposition has been developed , . The circuit is recursively decomposed into loosely connected subcircuits. The lowest-level subcircuits are an- alyzed separately and the resulting symbolic expressions are combined according to the decomposition hierarchy.

This results in the global nested expression for the complete circuit, which is much more compact than the expanded expression. The CPU time increases about linearly with the circuit size, provided that the coupling between the different subcircuits is not too strong. Another compact representation of symbolic expressions was presented recently. Following the use of binary decision diagrams in logic synthesis, determinant decision diagrams (DDD) have been proposed as a technique to canonically represent determinants in a compact nested format . The advantage is that all oper- ations on these DDDs are linear with the size of the DDD, GIELEN AND RUTENBAR: COMPUTER-AIDED DESIGN OF ANALOG AND MIXED-SIGNAL INTEGRATED CIRCUITS but the DDD itself is not always linear with the size of the circuit. This technique has been combined with hierarchical analysis in . Further investigation will have to prove the usefulness of this technique in practice.

Based on the many research results in this area over the last decade, it can be expected that symbolic analysis techniques will soon emerge in the commercial EDA marketplace and that they will soon be part of the standard tool suite of every analog designer. In the meantime, new (possibly heuristic) algorithms for the symbolic analysis of transient and large- signal circuit characteristics are currently being developed in academia.

Analog Circuit Synthesis And Optimization

The first step in the analog design flow of Fig. 4 is analog circuit synthesis, which consists of two tasks: topology se- lection and specification translation. Synthesis is a critical step since most analog designs require a custom optimized design and the number of (often conflicting) performance re- quirements to be taken into account is large. Analog circuit synthesis is the inverse operation of circuit analysis. During analysis, the circuit topology and the subblock parameters (such as device sizes and bias values) are given and the re- sulting performance of the overall block is calculated, as is done in the SPICE simulator. During synthesis, on the other hand, the block performance is specified and an appropriate topology to implement this block has to be decided first. This step is called topology selection. Subsequently, values for the subblock parameters have to be determined, so that the final block meets the specified performance constraints. This step is called specification translation at higher levels in the de- sign hierarchy, in which case performance specifications of subblocks have to be determined, or circuit sizing at the de- vice level, in which case the sizes and biasing of all devices have to be determined. See Fig. 7 for an illustration of this flow for low-level cells. The inversion process inherent to synthesis, however, is not a one-to-one mapping, but typi- cally is an underconstrained problem with many degrees of freedom. The different analog circuit synthesis systems that have been explored up till now can be classified based on how they perform topology selection and how they eliminate the degrees of freedom during specification translation or cir- cuit sizing. In many cases, the initial sizing produces a near optimal design that is further fine-tuned with a circuit op- timization tool. The performance of the resulting design is then verified using detailed circuit simulations with a simu- lator such as SPICE, and when needed the synthesis process is iterated to arrive at a close-fit design. We will now discuss the two basic steps in more detail.

1) Topology Selection: Given a set of performance spec- ifications and a technology process, a designer or a synthesis tool must first select a circuit schematic that is most suitable to meet the specifications at minimal implementation cost (power, chip area). This problem can be solved by selecting a schematic from among a known set of alternative topologies such as stored in a library (topology selection), or by gen- erating a new schematic, for example by modifying an ex- isting schematic. Although the earliest synthesis approaches Fig. 7.

Basic flow of analog circuit synthesis for a basic cell: topology selection and circuit sizing. considered topology selection and sizing together, the task of topology selection has received less attention in recent years, where the focus was primarily on the circuit sizing. Finding the optimal circuit topology for a given set of performance specifications is rather heuristic in nature and brings to bear the real expert knowledge of a designer. Thus, it was only natural that the first topology selection approaches like in

Oasys , Blades , Or Opasyn Were Rather

heuristic in nature in that they used rules in one format or an- other to select a proper topology (possibly hierarchically) out of a predefined set of alternatives stored in the tool’s library.

Later approaches worked in a more quantitative way in that they calculate the feasible performance space of each topology that fits the structural requirements, and then compare that feasible space to the actual input specifications during synthesis to decide on the appropriateness and the ordering of each topology. This can for instance be done using interval analysis techniques or using interpolation techniques in combination with adaptive sampling . In all these programs, however, topology selection is a separate step. There are also a number of optimization-based ap- proaches that integrate topology selection with circuit sizing as part of one overall optimization loop. This was done using a mixed integer-nonlinear programming formulation with Boolean variables representing topological choices , or by using a nested simulated evolution/annealing loop where the evolution algorithm looks for the best topology and the annealing algorithm for the corresponding optimum device sizes . Another approach that uses a genetic algorithm to find the best topology choice was presented in DARWIN . Of these methods, the quantitative and optimization-based approaches are the more promising developments that address the topology selection task in a deterministic fashion as compared to the rather ad-hoc heuristic methods.

2) Analog Circuit Sizing: Once an appropriate topology has been selected, the next step is specification translation, where the performance parameters of the subblocks in the se- lected topology are determined based on the specifications of the overall block. At the lowest level in the design hierarchy, this reduces to circuit sizing where the sizes and biasing of all devices have to be determined such that the final circuit meets the specified performance constraints. This mapping from performance specifications into proper, preferrably optimal, device sizes and biasing for a selected analog circuit topology

(B)

Fig. 8. The two basic approaches toward analog circuit synthesis: (a) the knowledge-based approach using procedural design plans, and (b) the optimization-based approach.

in general involves solving the set of physical equations that relate the device sizes to the electrical performance param- eters. However, solving these equations explicitly is in gen- eral not possible, and analog circuit sizing typically results in an underconstrained problem with many degrees of freedom.

The two basic ways to solve for these degrees of freedom in the analog sizing process are either by exploiting analog design knowledge and heuristics, or by using optimization techniques. These two basic methods, which are schemati- cally depicted in Fig. 8, correspond to the two broad classes of approaches adopted toward analog circuit synthesis, i.e., the knowledge-based approaches and the optimization-based approaches , .

A) Knowledge-Based Analog Sizing Approaches: The

first generation of analog circuit synthesis systems presented in the mid to late 1980s were knowledge-based. Specific heuristic design knowledge about the circuit topology under design (including the design equations but also the design strategy) was acquired and encoded explicitly in some com- puter-executable form, which was then executed during the synthesis run for a given set of input specifications to directly obtain the design solution. This approach is schematically illustrated in Fig. 8(a). The knowledge was encoded in dif-

The Idac Tool Used Manually Derived And Prear-

ranged design plans or design scripts to carry out the circuit sizing. The design equations specific for a particular circuit topology had to be derived and the degrees of freedom in the design had to be solved explicitly during the development of the design plan using simplifications and design heuristics.

Once the topology was chosen by the designer, the design plan was loaded from the library and executed to produce a first-cut design that could further be fine-tuned through local optimization. The big advantage of using design plans is their fast execution speed, which allows for fast-per- formance space explorations. The approach also attempts to take advantage of the knowledge of analog designers.

IDAC’s schematic library was also quite extensive, and it included various analog circuits such as voltage references, comparators, etc., besides operational amplifiers. The big disadvantages of the approach are the lack of flexibility in the hardcoded design plans and the large time needed to acquire the design equations and to develop a design plan for each topology and design target, as analog design heuristics are very difficult to formalize in a general and context-independent way. It has been reported that the creation of a design script or plan typically took four times more effort than is needed to actually design the circuit once. A given topology must therefore at least be used in four different designs before it is profitable to develop the corresponding design plan. Considering the large number of circuit schematics in use in industrial practice, this large setup time essentially restricted the commercial usability of the IDAC tool and limited its capabilities to the initial set of schematics delivered by the tool developer. Also, the integration of the tool in a spreadsheet environment under

The Name Planframe Did Not Fundamentally Change

this. Note that due to its short execution times, IDAC was intended as an interactive tool: the user had to choose the topology him/herself and also had to specify values for the remaining degrees of freedom left open in the design plan.

Oasys Adopted A Similar Design-Plan-Based Sizing

approach where every (sub)block in the library had its own handcrafted design plan, but the tool explicitly introduced hi- erarchy by representing topologies as an interconnection of subblocks. For example, a circuit like an opamp was decom- posed into subcircuits like a differential pair, current mirrors, etc., and not represented as one big device-level schematic as in IDAC. OASYS also added a heuristic approach toward topology selection, as well as a backtracking mechanism to recover from design failures. As shown in Fig. 9, the com- plete flow of the tool was then an alteration of topology se- lection and specification translation (the latter by executing the design plan associated with the topology) down the hier- archy until the device level is reached. If the design does not match the desired performance characteristics at any stage in this process, OASYS backtracks up the hierarchy, trying al- ternate configurations for the subblocks. The explicit use of hierarchy allowed to reuse design plans of lower-level cells while building up higher-level-cell design plans and, there- fore, also leveraged the number of device-level schematics covered by one top-level topology template. Although the tool was used successfully for some classes of opamps, com- parators and even a data converter, collecting and ordering all the design knowledge in the design plans still remained a huge manual and time-consuming job, restricting the prac- tical usefulness of the tool. The approach was later adopted in the commercial MIDAS system , which was used suc- cessfully in-house for certain types of data converters. Also,

Azteca And Catalyst Use The Design-Plan Ap-

proach for the high-level design of successive-approximation and high-speed CMOS data converters, respectively. Inspired GIELEN AND RUTENBAR: COMPUTER-AIDED DESIGN OF ANALOG AND MIXED-SIGNAL INTEGRATED CIRCUITS Fig. 9.

Hierarchical alternation of topology selection and specification translation down the design hierarchy. by artificial intelligence research, also other ways to encode the knowledge have been explored, such as in BLADES , which is a rule-based system to size analog circuits, in ISAID , or in .

In all these methods, the heuristic design knowledge of an analog designer turned out to be difficult to acquire and to formalize explicitly, and the manual acquisition process was very time consuming. In addition to analytic equation-based design knowledge, procedural design knowledge is also required to generate design plans, as well as specialized knowledge to support tasks such as failure handling and backtracking. The overhead to generate all this was too large compared to a direct design of the circuit, restricting the tools basically to those circuits that were delivered by the tool developers. Their coverage range was found to be too small for the real-life industrial practice and, therefore, these first approaches failed in the commercial marketplace.

b) Optimization-Based Analog Sizing Approaches: In order to make analog synthesis systems more flexible and ex- tendible for new circuit schematics, an alternative approach in a second generation of methods, the optimization-based approaches. These use numerical optimization techniques to implicitly solve for the degrees of freedom in analog design while optimizing the performance of the circuit under the given specification constraints. These strategies also strive to automate the generation of the required design knowledge as much as possible, e.g., by using symbolic analysis tech- niques to automatically derive many of the design equations and the sizing plans, or to minimize the explicitly required design knowledge by adopting a more equation-free simula- tion-oriented approach. This optimization-based approach is schematically illustrated in Fig. 8(b). At each iteration of the optimization routine, the performance of the circuit has to be evaluated. Depending on which method is used for this per- formance evaluation, two different subcategories of methods can be distinguished.

In the subcategory of equation-based optimization ap- proaches, (simplified) analytic design equations are used to describe the circuit performance. In approaches like

Opasyn And Staic , The Design Equations Still

had to be derived and ordered by hand, but the degrees of freedom were resolved implicitly by optimization. The

Optiman Tool Added The Use Of A Global Simulated

annealing algorithm, but also tried to solve two remaining to automate the derivation of the (simplified) analytic design equations needed to evaluate the circuit performance at every iteration of the optimization . Today, the ac behavior (both linear and weakly nonlinear) of relatively large circuits can already be generated automatically. The second problem is then the subsequent ordering of the design equations into an application-specific design or evaluation plan. Also, this step was automated using constraint programming techniques in the DONALD tool . Together with a sep- arate topology-selection tool based on boundary checking and interval analysis and a performance-driven layout generation tool , all these tools are now integrated into the AMGIE analog circuit synthesis system that covers the complete design flow from specifications over topology selection and circuit sizing down to layout generation and automatic verification. An example of a circuit that has been synthesized with this AMGIE system is the particle/ra- diation detector front end of Fig. 10, which consists of a

-Stage

pulse-shaping amplifier (PSA). All opamps are complete circuit-level schematics in the actual design as indicated in the figure. A comparison between the specifications and the performances obtained by an earlier manual design of an expert designer and by the fully computer-synthesized circuit is given in Table 2. In the experiment, a reduction of the power consumption with a factor of 6 (from 40 to 7 mW) was obtained by the synthesis system compared to the manual solution. Also, the final area is slightly smaller. The layout generated for this example is shown in Fig. 11.

The technique of equation-based optimization has also

Modula-

tors in the SD-OPT tool . The converter architecture is described by means of symbolic equations, which are then used in a simulated-annealing-like optimization loop to derive the optimal subblock specifications from the specifications of the converter. Recently, a first attempt was presented toward the full behavioral synthesis of analog systems from an (annotated) VHDL-AMS behavioral de- scription. The VASE tool follows a hierarchical two-layered optimization-based design-space exploration approach to

Authors:

Peder EZ Larson 1, 2,* , Jenna ML Bernard1, James A Bankson 3, Nikolaj Bøgh 4, Robert A Bok1, Albert P. Chen 5, Charles H Cunningham 6,7, Jeremy Gordon1, Jan-Bernd Hövener 8, Christoffer Laustsen 4, Dirk Mayer 9,10, Mary A McLean11 12, Franz Schilling13, James Slater1, Jean-Luc Vanderheyden5, 14, Cornelius von Morze 15, Daniel B Vigneron1, 2, Duan Xu1, 2, and the HP 13C

94143, Usa.

Denmark. 5 GE Healthcare, Menlo Park, California, USA. 6 Physical Sciences, Sunnybrook Research Institute, Toronto, Ontario, Canada.

8 Section Biomedical Imaging, Molecular Imaging North Competence Center (MOIN CC), Medicine, Baltimore, MD, USA. Cambridge, United Kingdom.

14Jlvmi Consulting Llc, Dousman, Wi, Usa

#See Acknowledgements for a list of all HP 13C MRI Consensus Group Members This work was supported by the ISMRM Hyperpolarized Media MR Study Group, the ISMRM Hyperpolarization Methods & Equipment Study Group, and the Hyperpolarized MRI Technology Resource Center (NIH/NIBIB grant P41EB013598).

Abstract

MRI with hyperpolarized (HP) 13C agents, also known as HP 13C MRI, can measure processes such as localized metabolism that is altered in numerous cancers, liver, heart, kidney diseases, and more. It has been translated into human studies during the past 10 years, with recent rapid growth in studies largely based on increasing availability of hyperpolarized agent preparation methods suitable for use in humans. This paper aims to capture the current successful practices for HP MRI human studies with [1-13C]pyruvate - by far the most commonly used agent, which sits at a key metabolic junction in glycolysis. The paper is divided into four major topic areas: (1) HP 13C-pyruvate preparation, (2) MRI system setup and calibrations, (3) data acquisition and image reconstruction, and (4) data analysis and quantification. In each area, we identified the key components for a successful study, summarized both published studies and current practices, and discuss evidence gaps, strengths, and limitations. This paper is the output of the “HP 13C MRI Consensus Group” as well as the ISMRM Hyperpolarized Media MR and Hyperpolarized Methods & Equipment study groups. It further aims to provide a comprehensive reference for future consensus building as the field continues to advance human studies with this metabolic imaging modality.

Keywords: Hyperpolarized MRI, metabolic imaging, carbon-13, pyruvate, dissolution dynamic

Introduction

MRI with hyperpolarized 13C agents, also known as hyperpolarized (HP) 13C MRI, has shown great potential as a novel imaging modality, particularly for its ability to probe metabolic processes in real time. The first human studies with HP [1-13C]pyruvate were performed in 2011 in prostate cancer patients (1).

Since then, there have been over 60 papers published with imaging results of human subjects from 13 different sites, with applications including prostate cancer, brain tumors, breast cancer, kidney cancer, pancreatic cancer, metastatic disease, liver disease, ischemic heart disease, diabetes and cardiomyopathies. The vast majority of these studies used [1-13C]pyruvate (1–63), where [2-13C]pyruvate (64) and 13C-urea (56) have been demonstrated too.

As clinical HP 13C MRI advances, there is a growing need to build consensus for best practices, which are critical for comparing data across sites, performing multi-site trials,deploying methods to new sites, partnering with vendors, and potentially for obtaining broader regulatory approvals.

In March 2022, we initiated an effort to build consensus within the HP 13C MRI community with this opportunity in mind, and it was greeted with strong enthusiasm. The “HP 13C MRI Consensus Group”, containing over 55 members from 27 sites, identified the area of greatest need and opportunity for consensus building to be HP [1-13C]pyruvate human

●

Pyruvate is the most mature and widely used HP agent and has the most significant translational evidence emphasizing the potential clinical impact.

●

Clinical trials, particularly multi-site trials, have the strongest need for consensus methods to ensure that data can be combined across sites. This work is a Position Paper for which the goal is to describe current successful practices and study methods for HP [1-13C]pyruvate human studies along with justification to support those practices. This is divided into four major topic areas: (1) HP 13C-pyruvate preparation, (2) MRI system setup and calibrations, (3) data acquisition and image reconstruction, and (4) data analysis and quantification (Fig. 1). The current successful practices and study methods include a literature review of published peer-reviewed journal papers showing human HP [1-13C]pyruvate study data, up to September 2022 (1–63), as well as new unpublished information from surveys of HP 13C study sites. Based on this information, we also highlight the evidence gaps, strengths, and limitations of current practices which are summarized at the end of each section.

Figure 1: Illustration of the HP 13C MRI human study process, including the 4 major areas covered in this paper: Hyperpolarized 13C-pyruvate preparation, MRI system setup and calibration, Acquisition and Reconstruction, and Data Analysis and Quantification.

Figure 2: Anatomical targets of HP [1-13C]pyruvate MRI human studies published up to September 2022.

Hyperpolarized 13C-Pyruvate Preparation

This section covers the processes for creating the HP agent, 13C pyruvate, and will include many aspects and considerations that are needed to safely and effectively prepare doses for metabolic imaging studies in human subjects. These include material, personnel, equipment and facility, fluid path preparation, quality control, and release.

It is helpful to understand that the specifications of a dose of 13C pyruvate suitable for in vivo MR HP metabolic imaging were shaped in part by early preclinical studies performed by GE HealthCare summarized in Ref. (65). In short, the safety of the two novel drug components, 13C pyruvate and the electron paramagnetic agent (EPA) AH111501, were demonstrated in those studies. The more precise formulation of the dose suitable for human use was then determined from clinical studies (66) that included two Phase 1 clinical trials in young and elderly healthy volunteers without hyperpolarization of the 13C nuclei and another Phase 1/2a dose escalation and imaging feasibility study with HP 13C pyruvate in 31 prostate cancer patients at the With the exception of the first HP 13C imaging clinical trial, which utilized a prototype device in a cleanroom (1), all HP 13C studies performed in humans to date have utilized the SPINlab polarizer (manufactured by GE HealthCare). Consequently all doses of the HP 13C pyruvate delivered by SPINlab have been produced using the “SPINlab Pharmacy Kit” that serves as the container-closure system for the various drug components (13C pyruvic acid and EPA mixture, dissolution medium, and neutralization and dilution medium) during sample polarization, dissolution and quality control (QC) processes. Thus many aspects of the HP sample preparation considerations discussed below are related to the SPINlab instrument and the consumables designed to be used with it (67).

General Considerations

While more than 860 patients or healthy subjects having been injected with HP 13C pyruvate as of January 2022 without reports of any serious adverse events (68), HP 13C pyruvate injection remains an investigational MR contrast agent and can only be administered by those with Investigational New Drug (IND) exemption from the Food and Drug Administration (FDA) in the USA, a Clinical Trial Application (CTA) in Canada, approval from National Research Ethics Committee Services in the UK, or approval from the relevant local regulatory body. Thus, methods and processes involved to produce a dose should have patient safety as the first priority. Since utilizing dissolution dynamic nuclear polarization (dissolution-DNP) for human use is still a relatively new development, there are no existing published regulatory guidelines specifically for this method.

There are two major production styles that determine how various sites approach the agent preparation. In the US, the most common approach is to rely on a sterilizing filter (“Terminal Sterilization”) to ensure sterility of the final product, akin to PET tracer production, where a starting molecule with a radioisotope is processed using various other ingredients to make the final, desired and injectable contrast agent within a necessarily short amount of time (69). For these sites, sterilization of the components and accessories upstream of this filter are not required, although many of them were manufactured and tested following Good Manufacturing Practice (GMP) or Good Laboratory Practice (GLP) requirements. The filling process is usually performed under an ISO 5 laminar flow hood, but a clean room or an isolator is not required.

This approach is typically accompanied by testing the integrity of the sterilizing filter prior to release of the dose for injection. Typically, post release endotoxin and sterility tests are performed using an aliquot reserved from each released dose.

In the UK and EU, the most common approach is to more-closely follow sterile pharmaceutical compounding guidelines (70), where all components and ingredients are required to be sterile or manufactured under GMP guidelines and are assembled and filled within a clean room environment or an isolator system (“Sterile Preparation”). Typically a batch of Pharmacy Kits for HP 13C pyruvate injection are prepared together. The sterility of the final dose is also ensured by batch validation testing, in addition to the sterility of the ingredients and the sterile compounding process. The endotoxin and sterility testing are performed for the process validation but are not performed for each injected dose.

Some institutions fill and assemble the Pharmacy Kit required for a specific study on the same day or the day prior to polarization, dissolution, and patient administration, but others have also demonstrated the feasibility of preparing a batch of kits, keeping them in a -20ºC freezer and using them over a period of a few months.

Beyond the obvious requirements that the process and the facility has to ultimately produce a dose that is safe to inject into a human, regulatory authorities will also focus on the question “Are you in control of your processes?”. To be in control of your process requires an in-depth and broad understanding of all processes involved in pre, post, and during the production process.

Personnel

It is typical and may be required to have licensed personnel involved in the production process depending on local regulations.Typically a pharmacist, radiopharmacist or other similarly qualified person (QP), in charge of the facility where the Pharmacy Kit filling and preparation is taking place, is responsible for the overall process and the release of the injectable dose.

Qualified cleanroom technicians are often involved in the Pharmacy Kit filling under the supervision of the pharmacist or QP. As is required for pharmaceutical compounding or PET tracer production, training requirements and training records for all personnel need to be maintained and available for audit by the FDA or equivalent.

Equipment And Facility

The facility and all equipment need to have standard operating procedures (SOPs) that describe how equipment is used, maintained, and calibrated to comply with relevant legislation. Currently, almost all the filling of the Pharmacy Kit takes place within a compounding laminar flow hood or isolator (typically ISO 5). At some sites, the filling is conducted within a cleanroom, while at others, it is conducted in a dedicated non-cleanroom space, reflecting differences in cleanroom approach and specifications between regulators worldwide (71). Some equipment or facilities, such as the compounding hood or cleanroom, may require external certified laboratories for testing.

Material Handling

Material handling guidelines (69,70) require SOPs detailing a system to track all of the materials involved in the HP production process for a particular patient dose, similar to current good manufacturing practice (cGMP) requirements for material handling for drug compounding. This includes acceptance standards, storage conditions, amount used in the patient dose for each ingredient and materials used in the assembly of the fluid path and Pharmacy Kit. Currently some users choose to open and inspect and sometimes modify the Pharmacy Kits upon arrival, but some users keep them in the sealed packaging until they are required for dose preparation.

Pharmacy Kit Filling And Assembling

As required by an IND or its equivalent, the preparation of the doses of HP 13C agent are detailed in the Chemistry, Manufacturing, and Control (CMC) section of an applicable regulatory submission; an example of this has been made available (72). It describes the processes of filling the Pharmacy Kit with the different components that make up the final drug product, and of assembling the final kit for either storage or immediate use in the polarizer. Special attention should be given to the laser welding process in order to satisfy installation qualification (IQ) and operational qualification (OQ). Typically, the final developed process is validated by process qualification (PQ) runs, during which 3 or more Pharmacy Kits are filled and used and the final HP 13C products are tested for endotoxin and sterility and to confirm that they meet the dose specifications for injections (usually including pyruvate concentration, residual EPA concentration, pH, liquid state polarization level and dose temperature). The data from 3 consecutive PQ runs are submitted as part of the IND submission (or its equivalent), and are often also reviewed by the Institutional Review Board (IRB) where the studies are conducted.

Quality Control And Dose Release

The quality control (QC) and dose release can be separated into two aspects: one is the QC and release of the filled Pharmacy Kit, and second is the QC and release of the HP 13C agent for injection, after polarization and dissolution. For institutions filling a batch of kits and storing them to use over a period of time, typically the batch can be released based on initial validation, environmental monitoring data from the day of kit production, and if filters are used during preparation of any of the components, filter integrity testing. But in some cases one or more kits are used for validation before the batch of kits are released for future use. For institutions that fill only the kits required for specific studies shortly before the experiment, the filled kits often do not go through separate release tests before they are used.

The quality control of the HP 13C pyruvate solution post dissolution is primarily performed to ensure that the agent meets the dose specifications (Table 1) before it is administered to the subject. These specifications target both safety (pH, residual EPA, temperature) and efficacy (pyruvate concentration, polarization, volume). Typically, the pyruvate concentration, residual EPA concentration, pH, dose temperature, dose volume, and liquid state polarization are measured by the QC accessory associated with the SPINlab polarizer. Some users perform a secondary measurement for one of the parameters, such as pH, using a different instrument or pH paper. For sites that do not go through a separate release testing process for batch filled kits, the integrity of the sterilization assurance filter, a part of the Pharmacy Kit, is typically tested as a part of the dose release. It is also common for these users to preserve an aliquot of the final HP 13C pyruvate solution for post-release endotoxin and sterility testing. This testing cannot be completed fast enough to test an individual dose prior to injection, but this is why other processes such as PQ runs and validation testing are done to minimize the chance a subject could be injected with a contaminated dose.

The Final Dose Release And Injection

should be done under the supervision of a licensed professional, based on local regulations.

Some Key Challenges

Many of the challenges associated with HP 13C pyruvate preparation can be attributed to the conditions required for the dissolution-DNP method of high magnetic field (~3-7 T) and very low temperature (~1 K) during polarization, with pressurized and superheated water necessary for the rapid dissolution event. These extreme conditions are quite challenging for the design of the container-closure and fluid path system. In particular, the cryogenic temperature in the polarizer requires special attention to any moisture or ambient (moist) air introduced into that portion of the fluid path, which can form an ice block at ~1 K. This ice can lead to flow restriction during the dissolution event and reduce the strength of the laser welded bond between the cryovial and its cap. This can ultimately produce failures in the dissolution step, including variations in final pyruvate concentration and pH that may fail to meet QC release criteria as well as fluid path ruptures that provide no available dose and result in polarizer down-time.

The polarization of the HP 13C pyruvate sample decays quickly over the span of a few minutes after dissolution, and thus the process of dissolution, QC for release, and injection should be completed as fast as possible to preserve the high polarization level achieved. Any delays in the preparation process, such as transportation time or equipment malfunction, can significantly reduce the final polarization and result in lower quality imaging data.

Current Practices

A summary of data collected from all sites performing clinical trials with HP 13C-pyruvate is shown in Fig. 3 and Table 1, including the specification of the final dose and how the quality control and release of the final dose are performed. There is a split in the Production Style, described in the General Considerations section above, with 8/13 sites using Sterile Preparation versus 5/13 using Terminal Sterilization. While many of the dose specifications show notable differences in acceptable ranges, all of these variations listed in tables have been successfully and safely been used to perform HP 13C pyruvate studies in humans. Their differences depend on the institutions’ preferences, resources and their particular regulatory situation. There is high similarity in pyruvate ranges, temperature ranges, EPA limits, and volume limits. There is modest variability in pH ranges and large variability in the endotoxin test limit. There is a 3-fold difference in acceptable polarization levels, which are measured to ensure a futile dose is not injected since the polarization is directly proportional to SNR. This reflects the decision by several sites to believe that useful data can be still be obtained with suboptimal polarizations.

Figure 3: Hyperpolarized agent preparation methods reported by sites currently performing HP

In House

Table 1: HP 13C-pyruvate preparation parameters, methods, and dose specifications used for quality control testing and release as well as validation. These were obtained from a survey of all sites performing clinical trials with HP [1-13C]pyruvate. The parameters used for product release are noted in bold text, otherwise these parameters are measured for batch validation or other QC measurements. The endotoxin and sterility testing are performed during process validation of the batch and/or post-injection, and largely depends on the agent production approach.

Summary

The overall safety record of HP 13C-pyruvate has been very strong, and the SPINlab hyperpolarizer has proven to provide high polarizations at human sized doses while meeting numerous QC and release criteria. A weakness remains the failure modes of the SPINlab Phamacy Kits (e.g. ice blocks, path ruptures), which are placed under extreme requirements particularly during dissolution. The preparation process still requires a high degree of expertise.

Therefore, there is a significant need to improve the reliability, robustness, and ease of operation for generating HP 13C-pyruvate doses for human studies. Furthermore, there is a divide between manufacturing and sterile compounding style preparation as well as other site-specific practices, resulting in variations in SOPs and justification required to relevant regulatory bodies. There have also been no comparisons between these approaches. It is also unclear what release criteria and QC parameters are truly required to ensure patient safety.

However, all of the reported methods are acceptable and approved by the appropriate regulatory authorities, and have led to the rapid expansion of successful human studies in recent years.

Mri System Setup And Calibrations

This section covers the MRI system setup, including the imaging system, RF coils, phantoms, and prescan calibration methods.

Imaging System

The main prerequisite for a given MRI scanner to be capable of supporting studies with HP 13C is its “broadband” capability to transmit and receive radiofrequency (RF) signal at the frequency of 13C, which is around 4 times lower than 1H. This does not come as a default on clinical MR devices. The transmit power of the broadband amplifier should also be sufficient to support the intended flip angle and RF pulse shape with the employed transmission RF coil(s) for 13C. Most studies to date use relatively low flip angles (< 90 degrees) for HP 13C in order to preserve polarization for time-resolved imaging. The capability to receive 13C signal on multiple channels is also desirable to increase SNR, as discussed further in the “RF coils” section.

The choice of magnetic field strength is primarily dependent on the metabolites’ frequency separation due to chemical shift dispersion and 1H imaging. High field strengths do not enhance hyperpolarized 13C signal as they do for 1H because the signal strength in a HP experiment relies on manipulating the population of quantum energy states outside of the MRI scanner.

However, the injected HP 13C-pyruvate and its metabolic products have greater frequency separation at higher fields, and it may thus be easier to separate and quantify these resonances at higher fields. This comes at the cost of a reduction in the achievable T2* and often reduced T1. As the initial polarization is independent of the imaging field strength it has been proposed that the increased T2* at 1.5T can potentially be exploited to increase SNR by adapting the acquisition bandwidth or reduce off-resonance imaging effects in cases when the decay of the transverse magnetization is dominated by T2* (73). In practice, 3T has been used in all published human 13C-pyruvate studies surveyed (Supporting Table S1), and comprises the majority of scanners currently in use for human studies (Table 3). A field strength of 3T is well-suited for 1H MRI anatomical reference and correlative imaging.

Stronger and more rapidly slewing magnetic field gradients support more rapid spatial encoding, particularly for metabolite-specific single-shot imaging using echo-planar imaging (EPI) or spiral imaging (See “Acquisition and Reconstruction”). Although the spatial resolution acquired for HP 13C imaging is typically much coarser than for 1H MRI, the factor of ~4 in gyromagnetic ratio leads to the same reduction factor in performance of the gradient system, so 13C experiments are potentially more limited by gradient hardware performance. To date, all human studies have used the commercially-available integrated gradient systems provided in clinical MRI scanners.

Optimization of scanner design has understandably focused on minimization of artifacts in 1H MRI, where devices such as room lights, the gradient amplifiers, and the motors driving the patient bed are checked to ensure that they do not produce RF interference at the 1H frequency, but artifacts may arise at other frequencies. Eddy current compensation is also not always appropriately adjusted for nuclei at other frequencies (74). In order to optimize for 13C, many sites have performed checks on phantoms for RF interference, gradient artifacts, and eddy currents (74), including the use of post-hoc gradient impulse response function characterisation and correction, and some vendors have fixed these issues as well.

Rf Coils

For HP 13C imaging studies in humans, RF coils for both 1H and 13C nuclei are needed, with 1H MRI providing an anatomical reference for registration and optional additional multiparametric MRI readouts. At the Larmor frequency of 13C nuclei, the relative contributions from coil noise compared to sample noise increase compared to 1H (73,75), although sample noise still is likely the dominant contributor for human-sized coils at 32.1MHz - the resonance frequency of 13C nuclei at 3T.

The key requirement for human 13C-pyruvate RF coils are that the coil geometry and sensitive volume must cover the volume of interest in the subject. Table 2 and Figure 4 shows coil configurations that have been used and optimized for applications in different anatomic regions.

Volume resonators are most commonly used for transmit, as they surround the subject to

Provide B1 Transmit Across The Fov (B1

+). While 1H relies on a large birdcage (“body”) coil built into the scanner, 13C transmit coils must be placed inside the bore. This takes up valuable space within the magnet, and also has led to the use of designs with relatively inhomogeneous

B1

+. Many human studies have used Helmholz pair resonators for transmit, including the “clamshell coil”, which has a notably inhomogeneous B1

+ Profile But Has Been Used Because Of

relatively easy integration into the scanner bore. B1

+ Variation Results In Variations In The Flip

angles that control the use of the hyperpolarized magnetization and creates errors in common HP metrics (9,76). The exception are head coils, where birdcage designs with highly

Homogeneous B1

+ can be placed around the head while easily fitting inside the bore. As with 1H MRI, higher SNR can typically be achieved by smaller receive coil elements, such as surface coils or phased arrays, and the majority of 13C receive coils used have layouts similar to 1H phased arrays.

RF coil quality control is important to ensure proper functioning of the coils to provide consistent imaging quality, especially with limited natural abundance 13C signal in vivo. It typically involves 1) a physical integrity check of the coil cables and connectors and 2) phantom SNR tests to check the coil’s performance and to monitor it over time (see Phantoms below). An useful reference for RF coil quality control is outlined in the MRI accreditation program of the American College of Radiology (77) and can be adapted for 13C coils.

Notably, configurations for brain and prostate studies used dual-tuned 1H/13C coil designs, which greatly simplify workflow and registration of 1H and 13C images, as no switching of coils is needed.

Table 2: RF coil configurations reported for human HP [1-13C]pyruvate studies.

Tx = Transmit

coil, RX = receive coil. The commonly used “clamshell” TX coil is a Helmholz pair design. For 1H RF configurations, all used the Body coil for TX unless otherwise noted, and “repositioned” indicates the 13C coil was removed for 1H imaging. One representative reference is listed for each configuration. The RF coil configurations reported in the reviewed papers are shown in Supporting Table S1.

Figure 4: Examples of RF coil configurations used for human HP [1-13C]pyruvate brain studies. (A,B) 13C Clamshell TX (Helmholz pair) and 2× 4-channel paddle RX arrays. (C) 13C Birdcage volume TX and 32-channel RX array (RX array slides into TX coil). (D) 13C Birdcage volume TX and 24-channel RX array, combined with a 1H 8-channel RX array. Image reproduced with permission from Ref (16).

Phantoms

Since hyperpolarized magnetization is non-renewable, phantoms containing 13C nuclei are important to: 1) test the multi-nuclear capabilities of the imaging system, including all parts of the signal excitation and receive chain; 2) perform calibration measurements before a scan with hyperpolarized nuclei; and 3) perform necessary pre-scan adjustments (see “Prescan Calibration” section). The phantoms currently in use are listed in Table 3. Their composition must provide sufficient 13C signal, with additional considerations of conductivity, stability, chemical shift(s) present, potential for dynamic imaging, and cost. The phantom geometries are typically either compact, in order to be used alongside the subject during a HP scan, or large enough to mimic the inner volume of a RF coil for system testing.

One popular compact design contains enriched 13C-urea at high concentration, typically 8 M, which provides a single resonance, placed inside a small container ~1 mL. The most common recipe mixes 13C-urea in a 90% water/10% glycerol solution, with glycerol used to increase the urea solubility and doping with a Gd-based contrast agent to shorten T1 which increases the potential SNR per unit time. For example, when Dotarem is added at a 3:1000 volume ratio the 13C-urea T1 is around 500 ms and T2 is around 100 ms. However, when testing pulse sequences influenced by T1 and T2, doping should be used carefully. This phantom is suitable for frequency calibration, transmit gain calibration, sequence testing, and as a fiducial marker when placed next to a patient. However, enriched 13C-urea has a relatively high cost compared to natural abundance compounds.

For larger volumes (>100 ml), the phantoms most often used contain undiluted ethylene glycol, glycerol, or dimethyl silicone. These compounds have sufficiently high carbon concentrations to provide sufficient 13C signal even with the 1.1% natural abundance of 13C. These larger phantoms matching the inner volume of an RF coil are useful for coil testing, including transmit

+) And Receive (B1

-) coil profile mapping, as well as to mimic acquisitions using in vivo FOV requirements. In this case, size and conductivity should match the expected subject size in order to mimic coil loading and get a realistic estimation of B1+. Large-volume natural abundance urea phantoms have also been used by some sites, but suffer from higher conductivity compared to biological tissues. Typically, it is easier to increase the conductivity and hence coil loading of the non-conductive phantom by adding NaCl to match physiological loading (16,78).

Dynamic phantoms that aim to mimic metabolite kinetics have also been developed (79–81), and have the potential to more closely mimic the HP experiment, but so far these are not widely used.

Prescan Calibration

Prior to performing an MRI acquisition, the so-called prescan procedure is used to set the shim parameters to maximize B0 homogeneity over the field of view (FOV) or a specific region of interest (ROI), the scanner center frequency (CF), the RF transmit gain, and the receiver gain.

While this calibration procedure is usually automated for 1H, the lack of sufficient natural abundance 13C signal prevents use of automated methods. (Although natural abundance 13C lipid signal has been detected, there are so far no reports on using this signal for prescan.) Table 3 shows current practices across sites.

Maximizing B0 homogeneity is independent of the nucleus and is therefore performed prior to 13C imaging using the 1H water signal and existing shimming tools, such as by a standard automated process (“Auto Shimming”) or using high order shimming routines. Similarly, the 13C CF can be calculated from the 1H CF using a predetermined scaling factor that depends on the target chemical shift (82). Another common approach used is to have a small, high-concentration 13C phantom, e.g. 8M 13C-urea, integrated in the RF coil or placed next to the scan subject (1). The reference frequency can also be based on real-time measurements after the HP injection but prior to imaging (83). Both the CF and B0 shimming are critical when using spectrally-selective RF pulses, as inmetabolite-specific imaging methods, where the desired excitation bandwidths are typically very narrow and frequency offsets can lead to a failure mode that is only apparent after injection.

The calibration of the RF transmit power is typically performed on a small, high-concentration 13C phantom placed near the region of interest during the scan or on a large 13C phantom of similar size and coil loading as the subject, prior to the subject scan. Reference power is often done by sweeping the power in a pulse-acquire sequence (53,62), or the Bloch-Siegert method (52,84). When using a small phantom, the location of the phantom, B1

+ Inhomogeneity As Well

as any shielding effects, e.g., when the phantom is integrated into a coil (1), may degrade the accuracy. Other methods include real-time Bloch-Siegert method measurements after the HP injection (83), and using the stronger natural abundance 23Na signal that is close enough to the 13C resonance frequency to be detected by 13C coils (82).

The receiver gain is predetermined, either systematically based on independent phantom measurements and assuming the dose and polarization of the HP compound is known prior to injection, or based on past HP imaging studies.

Power [Kw]

Phantom(s) - during study Phantom(s) - before study 13C Frequency

13C-bicarbonate doped with dimethyl silicone, various

Maximum Values

Table 3: Summary of the imaging systems, phantoms, and prescan procedures used at sites currently performing HP 13C-pyruvate human studies. These were obtained from a survey of all sites performing clinical trials with HP [1-13C]pyruvate. *Previously performed studies with a Siemens 3T Tim Trio. The imaging systems, phantoms, and prescan procedures reported in the reviewed papers are shown in Supporting Table S1.

Summary

Commercially available 3T MRI systems are by far the most commonly used for human HP 13C-pyruvate studies, although a systematic investigation of the impact of B0 has only recently been investigated (73). The multi-nuclear RF transmit and receive chain has proven sufficient for current acquisition strategies, although many sites have observed artifacts due to RF interference, gradient interference, and residual eddy currents when operating at the 13C frequency. A variety of 13C RF coils, tailored for numerous anatomical targets, have been successfully demonstrated, with the main limitation that most transmit coils take up a lot of additional space inside the bore and provide relatively inhomogeneous B1

+ Profiles. The

phantoms used have converged into generally 2 categories - small phantoms containing 13C-enriched compounds that can be used during the study and human-sized phantoms containing compounds with high carbon concentrations but without 13C enrichment that are used to test and calibrate the coils. There are no standardized compositions or geometry, and dynamic phantoms that recapitulate in vivo kinetics would be desirable but are still an emerging area. Prescan calibration procedures were not well defined in most publications, so we surveyed individual sites to determine current practices. Calibration procedures for the B0 field (13C CF and shimming) for most sites take advantage of 1H signal and methods, while methods

For Calibration Of B1

+ is more variable across sites, likely a reflection of remaining challenges in how to perform this calibration. Standardization of both phantoms and calibration procedures would synergistically improve the robustness and reproducibility of HP 13C studies.

Acquisition And Reconstruction

Data acquisition strategies in human HP [1-13C]pyruvate MRI studies must account for multiple chemical shifts, efficiently utilize the non-renewable HP magnetization, and acquire data quickly relative to metabolism and relaxation decay processes. These studies require spectral encoding to separate metabolites, necessitating pulse sequences that efficiently encode up to 5D data (3 spatial + 1 spectral + 1 temporal dimension). RF pulses must efficiently sample without immediately saturating the non-renewable HP magnetization, and sequences must acquire data quickly and be robust to both experimental and physiologic variation (e.g. B1

+ Inhomogeneity,

variation in perfusion) to ensure reproducibility and minimize scan-to-scan variability. This section covers current successful practices for data acquisition in human [1-13C]pyruvate studies, and accompanying 1H imaging, from different anatomic regions, including scan parameters and image reconstruction.

Acquisition And Reconstruction Methods

The acquisition methods used in human [1-13C]pyruvate studies can be classified into 3 categories: 1) MR spectroscopy or MR spectroscopic imaging (“MRS/I”), 2) chemical shift encoding methods, and 3) metabolite-specific imaging (Fig. 5).

Mrs/I Methods Specifically

resolve a spectrum that can be analyzed to extract expected as well as unexpected resonances, making this approach very robust. It was used in many initial studies (1).

Chemical Shift

encoding methods, most commonly the Iterative Decomposition of water and fat with Echo Asymmetry and Least-squares estimation (IDEAL) method, use imaging sequences acquired with multiple TEs and rely on a model-based separation of expected chemical shifts (85).

Metabolite-specific imaging methods use specialized RF pulses that are spatially and spectrally selective to excite individual metabolites which are then typically imaged with fast k-space trajectories such as echo planar imaging (EPI) or spirals (86).

Their Application To Different

organ systems is described below. The image reconstruction methods used in human [1-13C]pyruvate studies have typically been conventional methods (e.g. FFT, non-uniform FFT, or equivalent). The incorporation of accelerated imaging and advanced reconstruction methods including parallel imaging (4,57,87) and compressed sensing (7) has also been applied in human studies for improved spatial resolution, temporal resolution and coverage, but have the potential for additional artifacts as well as SNR losses due to ill-conditioning of the reconstruction (e.g. g-factor).

The Majority Of

published studies do not use accelerated imaging indicating the resolution and coverage achievable without acceleration is currently adequate for successful data collection. Performing coil combination, even with fully sampled data has also been shown to have specific challenges for HP human images: using naive sum-of-squares methods suffer from high noise amplification in the relatively low SNR regime of HP [1-13C]pyruvate (compared to 1H), motivating several HP 13C-specific methods that include data-driven coil sensitivity estimation which have shown obvious improvements over sum-of-squares (11).

More recently denoising techniques have been applied as post-processing of human HP data(41,42,44). The techniques applied are based on spatial-temporal singular value decomposition for unsupervised estimation of signal and noise components. They have shown improvements in apparent SNR in the brain and liver, while care must be taken to choose parameters such as the rank threshold to avoid oversmoothing and overfitting to the estimated signal components.

Prostate Studies

Prostate cancer was the first human application of HP [1-13C]pyruvate (1), and data was acquired with MRS/I methods: 1D dynamic MRS, single-slice 2D dynamic echo-planar spectroscopic imaging (EPSI), and single time point 3D EPSI. Advances in imaging strategies led to the development and application of new acquisition schemes, including undersampled 3D EPSI with compressed-sensing (7), model-based chemical shift encoding methods that use a priori information (47,59), and metabolite-specific EPI (10), all of which can provide volumetric whole-organ coverage and dynamic acquisitions.

The pyruvate bolus arrival in the prostate can vary by ± 10 s between patients, necessitating dynamic imaging to reliably and consistently capture the pyruvate bolus (18). For this reason, all currently ongoing studies acquire dynamic data. While MRS/I, chemical shift encoding, and metabolite-specific imaging can all achieve dynamic imaging, chemical shift encoding and metabolite-specific imaging provide greater dynamic and volumetric coverage (85). For scan prescriptions, the FOV is designed to provide full prostate coverage and typically to match the orientation of the anatomic imaging used for registration. Flip angles used in current studies are constant through time, as quantification with a variable-through-time flip scheme is highly sensitive to bolus timing (8) and errors in the RF transmit (B1 +) field (76).

Heart Studies

Data acquisition methods for 13C imaging in the heart must be designed to meet the demands of significant cardiac motion and blood flow. To cope with the periodic cardiac motion, most human heart studies to date used gating to the diastolic window, the longest cardiac cycle interval, which has reduced motion (2,22,28,30,35,36,38,45,52). The duration of the diastolic window limits the available data sampling time, making cardiac acquisitions the most time-constrained of the HP 13C MRI applications. The most common acquisition approach is metabolite-specific imaging with spiral k-space trajectories (2). Their single-shot imaging capability makes these methods particularly robust to motion effects. Furthermore, spiral k-space trajectories provide rapid k-space coverage and relatively benign flow and motion artifacts. The majority of studies have used 2D multi-slice acquisitions, but 3D encoding has also been used successfully (35).

Brain Studies

For HP 13C MRI of the human brain, the majority of studies have also used 2D (slice selective) acquisitions (10–12,14,16,28,33,40,41,44,51,53,60), with a trend toward volumetric coverage using 2D multi-slice metabolite-specific imaging. 3D metabolite-specific imaging of the whole brain, with phase encoding of the slice direction (34,57), has been shown to provide similar SNR efficiency (88) compared with multislice imaging. A number of studies have employed MRS/I (5,6,29,31–33,50,55) resulting in a spectrum from each voxel, which has the advantage of not requiring a priori information about which peaks to encode. This was important in early brain studies when it was not known which peaks would be detectable. Chemical shift encoding, using a set of images with different echo times and an iterative reconstruction of the individual resonances (i.e. the IDEAL approach (85)), has also been used (12,49,54), with the drawback that coverage in the slice direction was limited due to the time required to acquire multiple echo time images.

Abdomen And Breast Studies

The fundamental approaches to data acquisition and reconstruction in the abdomen and breast are largely similar to the aforementioned applications, but demand attention to particular challenges associated with these anatomic regions, especially relating to respiratory motion.

Although it has been shown that a basic 2D MRSI approach based on phase encoding and FID readout can be successfully applied for HP 13C imaging in breast (15) and kidney (13), major advantages in terms of spatiotemporal resolution and coverage have been realized using tailored approaches based on metabolite-specific imaging (43,62) and chemical shift encoding (43), which have facilitated multi-slice or 3D dynamic acquisitions over large FOVs in the abdomen (4,37,46).

The significant respiratory motion encountered in these regions can directly blur 13C images, and has further favored these rapid acquisition strategies. Motion also degrades B0 homogeneity, which can shift frequency-selective excitation profiles and introduce artifacts into rapid imaging readouts. This makes accurate determination of the acquisition center frequency and shimming essential in these regions which often cover large FOVs. (See “Prescan Calibration” section for more information). In some studies, breath-holding was used to minimize motion effects and enforce frame-to-frame data consistency (42). A pragmatic and reasonably effective approach for dealing with respiratory motion during 13C data acquisition is an initial breath-hold (as long as can be tolerated), followed by free-breathing (46,62).

1H Imaging

Collection of 1H imaging data is essential both for prescribing the 13C acquisition and for interpretation of the resulting 13C data. Multi-planar 1H scouts are acquired prior to 13C acquisition to enable graphical prescription of the 13C imaging region. All human HP 13C-pyruvate imaging studies acquire conventional MRI scans (e.g. T1- and T2-weighted volumes) for anatomic reference, aiming to cover at least the full 13C FOV. Acquiring these anatomic scans as close as possible to the time of 13C imaging (immediately before or after) minimizes potential misregistration between the data sets. Depending on the application, other advanced 1H sequences are also acquired (e.g. diffusion-weighted imaging for cancer imaging).

When contrast-enhanced data is acquired, it is done after 13C imaging, as paramagnetic contrast agents will accelerate 13C relaxation.

Reported Study Parameters

Figures 5 and 6, and Supporting Table S2 shows the reported acquisition study parameters for human HP [1-13C]pyruvate studies published as of September 2022. Figure 5 shows a mixture of MRS/I, metabolite-specific imaging, and chemical shift encoding methods have been successfully used, where spectroscopy-based methods have become less prevalent in recent studies. Figure 6 shows the acquisition timing, including the important start time and interval/temporal resolution, is quite variable across studies.

Figure 5: Acquisition methods used in published HP [1-13C]pyruvate human studies published up to September 2022, classified into: MR spectroscopy and spectroscopy imaging (MRS/I); chemical shift encoding methods, such as IDEAL, that use multiple TEs and model-based reconstructions; and metabolite-specific imaging methods that use spectrally-selective excitation to image a single resonance at a time.

Figure 6: Temporal acquisition characteristics reported in HP [1-13C]pyruvate human studies published up to September 2022. (a) Reported referencing of acquisition start times.

(B)

Acquisition start times reported when using dynamic imaging and when timing was reported relative to the end of the injection. (c) Temporal resolutions. “Not Applicable” indicates dynamic imaging was not used.

Summary

Three general categories of acquisition strategies have been used successfully for human HP 13C-pyruvate studies: MRS/I, model-based chemical shift encoding (e.g. IDEAL) methods, and metabolite-specific imaging methods. These have enabled successful studies in the prostate, heart, brain, abdomen, and breast. Recent studies increasingly have used the imaging-based strategies of metabolite-specific imaging and chemical shift encoding which are the fastest methods, although a heads-to–head comparison between techniques has not been performed.

Metabolite-specific imaging is quite popular because of its speed and compatibility with single-shot imaging, but is sensitive to B0 field variations and thus requires careful calibrations. Nearly all studies surveyed acquired data dynamically, allowing measurement of the bolus and metabolite kinetics. The exact timings and associated flip angles vary quite widely across reported studies, with no consensus yet as to how to choose these parameters. Image reconstruction is typically done directly using Fourier Transform methods, and accelerated imaging strategies are uncommon.

Data Analysis And Quantification

This section covers the analysis of data from human HP [1-13C]pyruvate studies, including modeling and metrics, visualization, as well as considerations for how to store data and metadata. Depending on study design, the analysis may need to give quantitative or semi-quantitative output reflecting a biological process or may just reflect a contrast between different regions of interest for quantitative evaluation.

Metrics

Figure 7: HP [1-13C]pyruvate raw data (A) have typically been quantified using four categories of metrics depending on the acquisition. Data acquired as a single time point are often quantified using normalized metabolite images or metabolite ratios (B). Dynamic data can be quantified using normalized metabolite images or metabolite ratios (B), or with metabolite timings such as time-to-peak (TTP) or pharmacokinetic (PK) models (C). The latter two require the data to be time-resolved. [1-13C]alanine and 13C-bicarbonate are analyzed similarly to [1-13C]lactate but omitted here for display.

Metabolite images are commonly used as summary metrics for HP MRI data, often including some form of normalization as well as summed over time as an area under the time curve (AUC) (17). These are analogous to the visual evaluation that is most used for routine clinical work (89,90). In these metabolite images, we expect that the [1-13C]pyruvate AUC signal is predominantly weighted towards perfusion and uptake, while [1-13C]lactate, [1-13C]alanine and 13C-bicarbonate AUCs represent metabolic conversion. The strength of this approach lies in its simplicity and relatively few underlying assumptions. Limitations to the use of single-metabolite images or AUCs include sensitivity to inhomogeneous coil profiles (57,87,91), the acquisition strategy and acquisition parameters, pyruvate polarization and concentration level, and signal relaxation rates (92). Further, the reader must be careful to interpret all the images in conjunction to better understand the underlying biology; for example, increased [1-13C]lactate in the presence of decreased [1-13C]pyruvate delivery can have a very different meaning compared to increased [1-13C]lactate with increased [1-13C]pyruvate delivery.

In an attempt to address variations in coil sensitivity, polarization level, and pyruvate delivery, AUC images are often computed by normalizing to a specified parameter, such as the maximum pyruvate or average lactate signals, or presented as a ratio such as lactate/pyruvate or divided by “total Carbon” - the sum total of HP 13C signal observed across all metabolites. The AUC ratios between metabolites and pyruvate are proportional to the corresponding forward kinetic rates (81,93), but are not directly comparable to rate constants when magnetization loss rates (e.g. relaxation and losses due to signal excitation) differ between studies. Similarly, the ratios between the produced metabolites (e.g. bicarbonate/lactate) can reflect the balance between downstream metabolic pathways (12,55). Care must be taken to consider how AUC images are calculated and normalized before comparing values between studies.

To further quantify the interpretation, pharmacokinetic (PK) modeling approaches were developed to compute the apparent kinetics of pyruvate-to-metabolite exchange (92,94–99). These yield semi-quantitative to quantitative apparent rate constants, given in s-1. Some models require a vascular input function, while others avoid this requirement (95). PK models can explicitly account for acquisition-specific details such as excitation angle and repetition time, and thus may reduce the effects of these details on quantification. An input-less model, provided in the Hyperpolarized-MRI-Toolbox (https://github.com/LarsonLab/hyperpolarized-mri-toolbox) (100) and thus frequently employed for human data, has been shown to fit well and robustly to prostate and brain data (8,20). PK models are quantitative in nature, arguably provide more relevant biological information (8,20), and appear to be reproducible across sites (51). However, rate constants derived from PK models are still apparent rates, and likely do not reflect a single biological characteristic.

Some additional considerations include whether complex or magnitude data is used, as the noise behaviors will impact the analysis differently. Additionally, cut-off thresholds or other criteria may be used to identify and avoid voxels with insufficient SNR before analysis to improve robustness (20,41).

Regardless of the analysis approach, the underlying biology is not always clearly represented by the data; instead, the metrics may be influenced by perfusion, barrier permeability, intercellular shuttles, enzyme activities, co-substrate concentrations, or combinations thereof, depending on the organ and disease of interest (19,43,94,101–103). This may be addressed by incorporating complementary information. As an example, HP 13C pyruvate data is influenced by perfusion, and thus addition of perfusion MRI could be important for interpretation (98,104,105).

All the methods outlined above have been explored in clinical studies, described in Supporting Table 3 and summarized in Figure 8. As of September 2022, approximately 52% of studies involving human subjects report rate constants derived from a PK model with a few different models reported. A nearly equal fraction (51%) of the studies report AUC ratio values.

Approximately 66% of these studies report metabolite-specific images or AUC values. About 40% report SNR values; this metric is particularly frequent in manuscripts that describe technical developments for clinical HP MRI. Approximately 16% of these studies summarize model-free metrics, and 10% report measurements from a single timepoint. Most studies report a combination of quantities.

Figure 8: Reported metrics used for analysis in HP [1-13C]pyruvate human studies published up to September 2022.

Visualization

A wide variety of approaches have been used for visualizing data from human HP 13C-MRI studies. The challenges and practical considerations are: 1) choosing the appropriate metrics to display, 2) how to encode the parameters (e.g. the colormap), and 3) choosing how to provide anatomical context and other multi-parametric data. The choice of visualization also depends on the goal which could be for diagnostic interpretation, but also quality control, reproducibility among readers and publication.

Metrics

The choice of HP 13C metrics is described in detail above. At this stage in HP 13C development where there is no standardized metric, often a combination of metabolite images and ratios or PK model parameters are shown.

Parameter Encoding

The mapping function chosen should provide an adequate, often quantitative, impression of the parameter mapped. There is a consensus in the visualization field that perceptually uniform maps are best suited to visualize continuous parameters, like the greyscale typically used by radiologists as well as other monochrome (black to blue) and color ranges (fire-type, rainbow-type) (106,107). Multi-color heatmaps have been the most frequently employed method for HP 13C data, while greyscale has infrequently been used but it ensures there is no coloring-based bias as well as facilitating later reuse (Fig. 9a). Among the color schemes employed in the clinical HP 13C literature, fire-type scheme seems to be the most common [similar to “Plasma” or “Inferno” in matplotlib.org]. Next most commonly employed is the rainbow-type scheme [similar to “Rainbow” in matplotlib.org].

Anatomical Context

HP MRI faces the challenge that it does not necessarily depict the anatomical features, similar to PET, and thus requires an anatomical reference. Most often, a grayscale anatomical image is overlaid with a HP colormap (Fig. 9c,d). This approach is very intuitive, but can skew perception as the grey-scale anatomical reference may affect the brightness of the HP data (e.g. signal in the skull). This bias does not occur when showing adjacent maps (Fig. 9a, b). Here, anatomical outlines may help to provide reference (Fig. 9b).

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