Compatible Platform for Reliable Cryogenic IC Design

Zhidong Tang1,5#, Zewei Wang1,2#, Yumeng Yuan1,2#, Chang He1, Xin Luo3, Ao Guo3, Renhe Chen1, Yongqi Hu1,2, Longfei Yang3, Chengwei Cao3, Linlin Liu3, Liujiang Yu4, Ganbing Shang4, Yongfeng Cao4, Shoumian Chen3, Yuhang

Zhao3, Shaojian Hu3, and Xufeng Kou1*(Senior Member, IEEE)

ShanghaiTech University, Shanghai, China, 2University of Chinese Academy of Sciences, Beijing, China, 3Shanghai IC Research and Development Center, Shanghai, China, 4Huali Microelectronics Corporation (HLMC), Shanghai, China, 5School of Integrated Circuits, Tsinghua University, Beijing, China. *Email: kouxf@shanghaitech.edu.cn; #Authors contributed equally to this work.

Abstract—This paper outlines the establishment of a generic of Cryo-CMOS. For instance, the scalable quantum processor

cryogenic CMOS database in which key electrical parameters and architecture requires the placement of the control, amplification, transfer characteristics of the MOSFETs are quantified as and readout modules adjacent to the quantum gate arrays so that functions of device size, temperature/frequency responses. the thermal noise and communication delay are minimized

Meanwhile, comprehensive device statistical study is conducted to

. Accordingly, various Cryo-CMOS-based digital/analog evaluate the influence of variation and mismatch effects at low temperatures. Furthermore, by incorporating the Cryo-CMOS integrated circuits (e.g., LNA, PLL, DAC, and ADC) have been developed to bridge the qubits and the user interface -. In compact model into the process design kit (PDK), the cryogenic 4 Kb SRAM, 5-bit flash ADC and 8-bit current steering DAC are addition, cryogenic electronics also play an important role in

designed, and their performance is readily investigated and aerospace exploration, medical and scientific applications, in optimized on the EDA-compatible platform, hence laying a solid which they can facilitate the design of low-noise sensors and foundation for large-scale cryogenic IC design. high-precision controllers -.

Index Terms—cryogenic device physics, temperature-dependent

compact model, Monte-Carlo simulation, process design kits, applications, it is of great importance to establish a generic cryogenic circuit design. platform that guides reliable and efficient cryogenic integrated circuit designs . In particular, such a Cryo-CMOS platform

I. INTRODUCTION should include sufficient characterizations of both transistors

and back-end-of-line (BEOL) components under low

C ryogenic CMOS (Cryo-CMOS) has shown great temperatures. Concurrently, the relevant device compact potential for enabling versatile energy-efficient models and process design kits (PDK) should maintain a high computing paradigms in the upcoming post-Moore era. accuracy in a wide temperature range. In this regard, while low- Due to the inherent improvements of MOSFET device temperature device physics has been investigated and relevant

performance at low temperatures in terms of enhanced driving Cryo-CMOS device models have been developed for various strength, smaller subthreshold swing, diminished leakage CMOS technology processes , yet the application of these current, and lower interconnect resistance, a fully Cryo-CMOS- cryogenic databases at the circuit/system level is still in its early enabled digital computer is projected to achieve a 3.4× higher development stage (e.g., most EDA tools still do not support

processing speed and or 37% reduction in power consumption circuit simulations below 2 K) . when operated at 7 K compared to the room-temperature performance . In the meantime, a 6T-SRAM bit-cell, which In this work, we present the establishment of a generic design is re-designed through the design-technology co-optimization platform for Cryo-CMOS applications. The cryogenic (DTCO) for 7 K operation, can boost the speed by 1.7× at a modeling flow includes the golden die selection, temperature-

fixed power budget (or save 80% power consumption at the dependent device DC/RF characterizations, key electrical same frequency) . Moreover, recent advancements in parameter extraction, and statistical device variation analysis, quantum computing have further broadened the research scope hence capturing the device electrical characteristics with varied

Manuscript received February 8, 2024. This work was supported by National Z. Wang, Y. Yuan, Y. Hu are also with Shanghai Institute of Microsystem Key R&D Program of China (2021YFA0715503, 2023YFB4404000), National and Information Technology, Chinese Academy of Sciences, Shanghai 200050, Natural Science Foundation of China (92164104), the Strategic Priority China. Research Program of CAS (XDA18010000), Shanghai Rising-Star Program X. Luo, A. Guo, L. Yang, C. Cao, L. Liu, S. Chen, Y. Zhao, and S. Hu are

(21QA1406000) and the Open Fund of State Key Laboratory of Infrared with the Shanghai IC Research and Development Center (ICRD), Shanghai Physics. Z. Tang, Z.W Wang and Y. Yuan contribute equally to this work. 201210, China. Tang, Z. Wang, Y. Yuan, C. He, R Chen, Y. Hu, and X. Kou are with L. Yu, G. Shang, and Y. Cao are with Huali Microelectronics Corporation School of Information Science and Technology, ShanghaiTech University, (HLMC), Shanghai 201314, China.

Shanghai 201210, China (e-mail: kouxf@shanghaitech.edu.cn). Z. Tang is also with the School of Integrated Circuits, Beijing Advanced Innovation Center for Integrated Circuits, Tsinghua University, Beijing 100084, China.

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Fig. 1. Illustration of cryogenic CMOS modeling flow. (a) Wafer mapping for golden die selection. (b) Temperature-dependent DC/RF device characterizations. (c) Generic Cryo-CMOS device compact model establishment. gate geometries, temperatures, and frequencies. Moreover, by Based on the experimental dataset and low-temperature integration the modified Cryo-BSIM compact model into the device physics, relevant cryogenic device SPICE models with PDK library, we demonstrate the design of three cryogenic semi-empirical formulas were subsequently generalized so that

digital (SRAM) and analog (ADC/DAC) circuit modules which key electrical parameters (e.g., threshold voltage, channel leverage the device-level operating mechanisms to achieve an mobility, and sub-threshold swing) in the entire examined optimized circuit performance at low temperatures. temperature/size region can be accurately described by one set of fitting parameters (i.e., model card). Concurrently,

II. CRYOGENIC CMOS DEVICE MODELING considering that the layout-dependent high-frequency RC

effects become indispensable for analog and RF IC design, we

Fig. 1 outlines the general Cryo-CMOS device resistive/capacitive/inductive components in reference to the

characterization and modeling flow adopted in this study. With equivalent small-signal MOSFET circuit model. Besides, in the help of the Automatic Test Equipment (ATE), the golden order to evaluate the impact of manufacturing process test die (i.e., whose electrical benchmarks are close to the fluctuations on device performance at cryogenic temperatures, process statistical average specifications at room temperature) a statistical model card, which consists of a set of random

was firstly selected from 4 Dies Under Test (DUTs) on the variables used for Monte-Carlo simulations, was developed wafer of the HLMC 40-nm technology node (Fig. 1a). Equipped based on the 4 DUTs data. with Lakeshore cryogenic probe station, the high-precision Keysight B1500A semiconductor device analyzer and the In addition to the front-end-of-line (FEOL) device study, the Keysight 5227A Vector Network Analyzer (VNA), we have back-end-of-line (BEOL) components (e.g., resistors,

developed a suitable cryogenic test platform which can cover capacitors, and interconnect) were characterized in the wide temperature (1 K – 3 K) and frequency (2 MHz – cryogenic temperature region to account for the parasitic effects

4 GHz) ranges. Accordingly, systematic device DC/RF on cryogenic integrated circuit simulations. Afterwards, the

measurements with respect to different temperatures and device SPICE models of transistors and relevant BEOL components sizes were carried out to ensure the full-scale Cryo-CMOS were incorporated into the generic cryogenic CMOS PDK device modeling (Fig. 1b). library. As a result, our established Cryo-CMOS platform could capture the temperature/frequency/geometric response of MOSFETs and extend the EDA simulation tool down to 1 K,

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hence providing a reliable guidance for the large-scale IC where µ is the long-channel low-field mobility at room design. In the following sub-sections, cryogenic MOSEFTs temperature, functions f and f represent the temperature- device modeling, statistical variation/mismatch analysis, as dependent scatterings and dimension-induced ballistic transport well as model validation will be discussed in detail. restriction effect, λ is the low-field mean free path, Eeff is the

B. Cryogenic Intrinsic MOSFET Device Modeling effective field associated with the surface roughness scattering, In the standard EDA simulation flow, model cards (i.e., and θ and θ are size-dependent fitting parameters. which are provided by foundries and include the technology 3) Instead of a simple linear correlation with the base process information such as oxide thickness, doping profile, temperature, the subthreshold swing (SS) is found to exhibit a

threshold voltage, and channel mobility) and netlists (i.e., saturation behavior at deep cryogenic temperatures (e.g., T < 4 which list the components in the circuit and the node connection K in our 4 nm-node devices), possibly due to the disorder- information) are functioned as input parameters in the model induced band tail broadening and the presence of localized simulator framework, and the output node information includes interface states near the band edge . In this regard, we have

voltage, current, and capacitance. In this context, the accuracy of the EDA simulator not only depends on the model cards, but introduced an effective temperature parameter Teff in the SS also relies on the device compact model framework that can model as: describe the electrical characteristics of MOSFETs. However, 𝑇+𝑇 +√(𝑇−𝑇 )2 +𝐷 most commercial models only support the temperature range of 𝑇eff = 2

(3) [2 K, 3 K], and they do not consider cryogenic device physics such as the Fermi level shift, phonon/ionized impurity where T is the critical temperature at which the impact of band- scatterings, carrier freeze-out, and band tail effect -. tail occurs, and D is the smoothing parameter.

To address such challenge, we have performed temperature- In conclusion, with the aforementioned modifications based dependent I-V characterizations of MOSFETs and confirmed on the original BSIM-4 framework, the updated key parameters that all nano-scale transistors would experience an increased in the model card were subsequently fitted in reference to the threshold voltage (VTH), enhanced channel mobility (μeff), and experimental data. As a result, the modified Cryo-BSIM model

steeper sub-threshold swing (SS) when the base temperature can accurately depict the DC transfer characteristics of all gradually drops to cryogenic temperatures. Based on the low- transistors across the device size chart on the golden die wafer temperature device physics, we have quantified the correlations from room temperature down to cryogenic temperatures, with between these electrical parameters and temperature. the average room-mean-square (RMS) values of the fitting error

Subsequently, we have proposed a modified Cryo-BSIM model all below 5%, as highlighted in Fig. 3. with three major changes including VTH(T), μeff(T), and Teff in the core BSIM-4 model, as re-captured as follows : 1) In general, the change of bulk carrier density (i.e., which causes the Fermi potential shift) and the broadened depletion width (i.e., which tailors the effective width and length of the inversion channel) lead to an enlarged VTH at low cryogenic temperatures . Accordingly, we have introduced the

temperature-driven gate geometry effects in the threshold voltage equation . Besides, the carrier freeze-out effect also changes the substrate resistance and leads to the re-distribution of the electric field in the bulk region, therefore bringing about a modified body effect-related term ∆𝑉BS (𝑇). Therefore, the overall threshold voltage correction term ΔVTH is given by Fig. 2. Cryogenic extensions to baseline BSIM-4 model. ∆𝑉TH (𝑇) = 𝑍 ∙ ∆𝑉TH,𝑊 (𝑇) + 𝐾 ∙ ∆𝑉TH,𝐿 (𝑇) + ∆𝑉BS (𝑇) (1) C. Cryogenic MOSFETs Variation Analysis

In addition to the individual device modeling, it is also

where ∆𝑉TH,𝑊 (𝑇) and ∆𝑉TH,𝐿 (𝑇) correspond to the narrow- critical to include a comprehensive statistical dataset, which width and short-channel effects, and the corresponding fitting accounts for the device performance variations caused by parameters Z and K denote their contributions, respectively. random process fluctuations, in the model card so that the high- 2) The drain current in the MOSFET device is closely precision EDA simulations of the designed integrated circuits

associated with the effective channel mobility μeff . Given are consistent with the tape-out test results . To meet the that both the ionization scattering and size limiting factor (i.e., requirement of a solid statistical analysis, we have further μeff  1/(1+20/L), where 0 is the low-field mean-free path) collected the temperature-dependent I-V data of MOSFETs would become the dominant factors at low temperatures, we from all DUTs with our cryogenic test platform, and generated

have proposed a semi-empirical effective mobility model the statistical model that incorporates both the global variation (i.e., die-to-die and wafer-to-wafer variations) and local 𝜇 (𝑇/298)−1.2 𝜇eff (𝑇) = 𝑓 (𝜆 ,𝐿)∙𝑓 (𝑇,𝐸 (2) mismatch variation (i.e., device-to-device variations on the 1 0 2 eff ,𝜃 ,𝜃 )

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same die) at cryogenic temperatures, as shown in Fig. 4. size corners (i.e., W/L = 0.1 µm/0.0 µm (small device), 1 µm/0.0 µm (short device), 0.1 µm/1 µm (narrow device), and 1 µm/1 µm (big device)). It is clear that the global variation (VTH) (i.e., which is defined as the standard deviation of the

PDF curve) progressively enlarges as the temperature

decreases, and the PDF statistical distribution curves become more broadened for the short-channel devices. By further counting 2 devices in total, the overall global threshold variation of ∆𝑉TH = 𝑉TH − ̅̅̅̅̅

𝑉TH is the average

value of VTH) increases by 10% when the base temperature drops from 2 K to 1 K, as visualized in Fig. 7.

Fig. 3. Cryogenic transfer characteristics of NMOS and

PMOS devices with validated model fitting.

Fig. 6. Probability density function of the threshold voltage

of NMOS devices with four different gate geometries at T =

2 K (red) and 1 K (blue), respectively.

Fig. 4. MOSFETs statistical model card.

To exemplify the evolution trend of the global variation

versus temperature, we have recorded the IDS-VGS results of the

MOSFETs from 4 DUTs across the whole wafer. As depicted

in Fig. 5, the transfer characteristics curves do display disparities among devices, and such variations become more pronounced in small-size transistors at low temperatures.

Fig. 7. Global variation statistics of VTH counted from a total

of 2 NMOS devices at (a) T = 2 K and (b) T = 1 K.

Moreover, since the differential pair structure has been

widely used in analog and RF circuits, any mismatch of the paired transistors caused by local stochastic fluctuations would degrade the circuit performance . Therefore, to examine the Fig. 5. Transfer characteristics of the NMOS devices with local MOSFETs mismatch scenario, the VTH values were (a) (W, L) = (0.1 m, 0.0 m) and (b) (W, L) = (1 m, 1 extracted from 5 transistors pairs on the same batch of the test- m) at T = 1 K and 2 K from 4 test dies. key, with varied gate aspect ratios ranging from W/L = 0.1

m/0.0 m to 1 m/1 m. As displayed in Fig. 8, both the T = Quantitatively, Fig. 6 summarizes the probability density 1 K and 2 K data follow the Pelgrom’s law of σ(∆VTH) = function (PDF) of the threshold voltage of NMOS devices at 4

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AVTH/√𝑊 · 𝐿 (i.e., where the slop AVTH represents the threshold properties), and the extrinsic RC-network associated with the voltage factor depending on the fabrication process) , yet ground-signal-ground (GSG) device layout structure (i.e., the characteristic value of AVTH increases by 78% when the which determines the input/output impedance, pole/zero transistors are cooled down from 2 K to 1 K, which indicates positions, as well as affects the high-frequency figure-of-merit

the worsened fluctuations of the doping profile at lower of the designed circuit). Afterwards, the measured S-parameter temperatures. data were transformed into the Y- and Z-parameter matrices, and the conventional Cold-FET method was adopted to extract the corresponding layout-dependent resistance and capacitance values. Meanwhile, temperature-dependent Short-Open-Load-

Through (SOLT) method (i.e., by using the standard GGBCS-5

calibration substrate) and Open-Short de-embedding technique were also conducted to exclude parasitic components from the instrument, cables, and on-chip interconnects/GSG pads .

Besides, we need to point out that the passive inductive

components do not show any temperature dependence, and we have hence treated them as a set of constants in the cryogenic RF device model.

Fig. 8. Pelgrom’s plots of the fitted σ(∆VTH) lines in reference

to the experiment data at T = 2 K and 1 K.

Based on these quantitative variation and mismatch results, we have completed the statistical model card files with additional temperature-dependent random variables in the

Cryo-BSIM framework. For example, we have introduced both

the calibrated σ(T) and AVTH(T) coefficients into the modified low-temperature threshold voltage variation model as VTH0= VTH0_typical + (1+σ(T))dVTH0_mis + (1+ AVTH(T))dVTH0_var (4) Fig. 9. Tracking plot of the VTH from 10 times Monte- where VTH0_typical is the reference mean value of the golden-die Carlo simulations at T = 2 K (red) and 1 K (blue). The device, while dVTH0_mis and dVTH0_var are the local mismatch and size of the transistor used in this figure is chosen as W/L =

global variation-associated random variables which both follow 0.1 m/0.0 m. the normal distribution relations. Consequently, the updated cryogenic PDK library is able to effectively cover the 1 K  T  2 K range. Fig. 9 illustrates the tracking plots from 10 times overall Monte-Carlo simulations (i.e., which include both the local mismatch and global variation). As a summary, the statistical study in this sub-section provides a trustworthy direction to mitigate the influence of the manufacturing

process-induced variation and mismatch effects by adopting appropriate device size engineering during the cryogenic circuit and system design.

CMOS devices, we have carried out temperature-dependent S-

parameter characterizations (from 0.2 to 4 GHz) on 3 multi- finger gate NMOS and PMOS devices across the device size chart of the HLMC 40-nm RF test wafer . As shown in Fig.

Fig. 10. Equivalent RF circuit of the Cryo-CMOS device

10, the equivalent small-signal equivalent circuit of the RF which includes the intrinsic MOSFET DC model and the

Cryo-CMOS device consists of the intrinsic MOSFET model

layout-dependent resistive and capacitive components. elaborated in Section II.B (i.e., which governs the DC electrical

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Fig. 1 summarizes the changes of extrinsic resistances and dependent electrical behaviors of such passive devices. As the capacitances as functions of temperature and frequency. base temperature gradually decreases, the resistances of all Owning to the degenerately-doped poly-silicon gate and silicide metallized diffusion and poly-Si types monotonically reduce Source/Drain area, both the gate electrode resistance Rg,ext and (Fig. 12a). In stark contrast, their non-metallized counterparts

Source/Drain terminal resistance Rs/d,ext become smaller with (SAB-type) is less susceptible to the temperature variation, the decrease of temperature, and such metallic-like R-T which could be invaluable for cryogenic bias circuit design (Fig. behaviors can be described by the 2nd-order polynomial 12b). Meanwhile, all interconnecting metal layers follow a equation R(T) = R(2 K)Teff,R, where Teff,R = A◊(T - 298)2 + universal metallic R-T behavior with a distinct resistance

reduction by more than 50% at T = 1 K (Fig. 12c). Such a B◊(T - 298) + 1, and the fitting parameters A and B are only salient feature could considerably enhance the energy dependent on materials . In view of the RF MOSFET- efficiency of the system at cryogenic temperatures. related capacitive components, their temperature-dependent Additionally, Fig. 12d reveals that the MOM capacitance of the slopes can be clearly divided into two categories. On the one BEOL technology remains almost constant regardless of the

hand, the metal routing capacitances (Cgs/gd,ext and Cds,ext) stay temperature variation, thus providing a quite stable reference almost unchanged with temperature, owning to their parallel for Cryo-CMOS analog and RF circuit design. plate capacitor nature. On the other hand, the diffusion capacitances (Cjs, Cjd) in the Source/Drain-to-bulk junctions can be modeled as 𝐶j (𝑇) = 𝐶j [1 + 𝜁(𝑇 − 298)]/ √1 − 𝑉𝑝𝑛 /𝜑bi (𝑇), where  is the fitting parameter affiliated

with the temperature correction term, Vpn is the applied voltage, and 𝜑bi (𝑇) is the built-in potential across the junction region. Therefore, after accomplishing the data fitting procedure (i.e., using the ICCAP software) for the cryogenic model card, the updated Cryo-BSIM library manages to cover the NMOS and PMOS devices in the 0.0 m  L  1 m, 1 K  T  2 K and 0.2 GHz  f  4 GHz region.

Fig. 12. Temperature dependence of the (a) metallized

resistors, (b) silicide block type resistors, (c) interconnecting and metal layers, and (d) MOM capacitors.

Fig. 11. Frequency-dependent (a) Cgs and (b) Cds extracted

from the S-parameter data with varied temperatures.

Temperature-dependent (c) Cj and (d) Rg,ext/Rs/d,ext of the RF

MOSFETs with W = 1 μm, L = 0.0 m, and Nf = 32.

E. Cryogenic Back-End-of-Line Device Characterization Fig. 13. Statistics of (a) VTH = VTH,10K - VTH,298K and (b) In addition to MOSFETs, the delineations of the BEOL relative IDS,10K/IDS,298K with NMOS and PMOS transistors components (e.g., resistors, capacitors, and interconnecting with four corner sizes. The error bars indicate the variation metal layers) are also of great importance for the cryogenic IC range of the experiment data collected from 4 test-dies,

design as they determine the interconnect delay, power while the solid dots represent the mean values used in the consumption, channel capacity, and the displacement/routing Cryo-CMOS model. strategy. Accordingly, Fig. 1 presents the temperature-

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The validation of the proposed cryogenic device model is to operate in the entire temperature region. Fig. 1 justifies presented in this sub-section. First of all, to minimize the device that the post-layout simulation results of these two circuits variation/mismatch-induced error, we have assigned the mean are in good agreement with the experimental taped-out data values of the threshold voltage (VTH) and on-state current (ID) from room temperature down to T = 1 K, again manifesting

as the reference points during the device modeling process, as the reliability of our cryogenic modeling strategy. highlighted in Fig. 13. Under such circumstances, although the device-to-device variation increases in the low-temperature III. CRYOGENIC CIRCUIT DESIGN BASED ON GENERIC CRYO- region (i.e., discussed in Section II.C), the relative root-mean- CMOS PLATFORM square deviation of the IDS-VGS curves between the Cryo-BSIM

compact model and the experimental data only slightly enlarges from RMS298K < 3% to RMS10K < 10% at T = 1 K, as visualized in Fig. 14a.

Next, given that the intrinsic trans-conductance (gm) and cut-

off frequency (fT) can be explicitly expressed as 𝑊 𝑔𝑚 (𝑇) ≈ 𝜇eff (𝑇)𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉TH (𝑇)) (5) 𝐿 𝑔𝑚(𝑇) 𝑓𝑡 (𝑇) = 𝑅 (𝑇)+𝑅𝑠(𝑇) 2𝜋[𝐶𝑔𝑠 (1+ 𝑑 )+𝐶𝑔𝑑 (1+(𝑅𝑑 (𝑇)+𝑅𝑠 (𝑇))(𝑔𝑚 (𝑇)+1/𝑟𝑜 )] 𝑟𝑜

where r is the small-signal output impedance of the device.

Accordingly, by successively substituting the temperature-

dependent eff(T), VTH(T), R(T), and C(T) models into the above equations, the resulting simulated fT-T results in Fig. 14b are highly consistent with the experimental values which are directly extracted from the |H21| plots.

Fig. 16. Schematic of the solid state-based quantum

computer architecture with integrated quantum control Fig. 14. (a) Relative RMS deviation of the IDS-VGS transfer system in a cryogenic environment. characteristics between the Cryo-CMOS compact model and the experimental data. (b) Comparisons of the temperature- After quantifying the low-temperature electrical properties of dependent cut-off freqency data from simulations and the CMOS transistors and BEOL components with the Cryo-

measurements. CMOS model, we have further applied the modified cryogenic

PDK library to guide the design and optimization of various

digital and analog integrated circuits for the emergent cryogenic electronic applications. For instance, in a scalable solid state- based quantum computer system illustrated in Fig. 16, the generation of entangled qubits is realized at a deep cryogenic temperature (e.g., T ≈ 1 mK), and the output signals of the quantum processor are typically in the form of mV-level pulses with the operating frequency in the [1 GHz, 2 GHz] range -. In this context, in order to maintain a high fidelity of

the output states, the complementary quantum control system is Fig. 15. Verification of the taped-out experiment results and preferred to be placed at 4.2 K (liquid helium)  T  7 K (liquid the post-layout simulation results of (a) 1501-stage RO and nitrogen) so that not only the thermal noise is reduced, but also (b) bandgap reference at different temperatures. the manipulation, conversion, and error correction of qubits can

be finished within the coherent time . Besides, it is also

Furthermore, the accuracy of our Cryo-CMOS model was

recommended to allocate a Cryo-SRAM memory in the same also verified at the circuit level. In particular, according to cryogenic temperature zone so as to minimize the propagation the cryogenic PDK library, we have designed a 1501-stage delay between the computing and storage modules. ring oscillator (RO) and a bandgap reference (BG) which aim

Following this general architecture, the cryogenic memory

module of the quantum computer was firstly designed.

Considering the driving strengths of the NMOS and PMOS

transistors change with temperature because of the mobility mismatch, we have re-adjusted the PMOS-to-NMOS gate-size ratio of the 6T SRAM bit-cell to optimize its drive capacity and static noise tolerance. Meanwhile, the peripheral circuitries (e.g., pre-charge stage, sense amplifier, and address decoder) have also been modified according to the cryogenic PDK library to ensure their correct functions down to 1 K. Fig. 17a shows the post-layout simulation results regarding the write/read dynamics and power dissipation of the cryogenic 4

Kb SRAM memory. From these data, we can subsequently take

full advantage of the EDA tool to facilitate the optimization process. As a result, the final taped-out 4 Kb Cryo-SRAM circuit indeed exhibits better performance in terms of speed and power consumption at low temperatures (Fig. 17b), and its quiescent supply current (IDDQ) benchmark is in good agreement with our model estimation (Fig. 17c).

Fig. 1 (a) Cryogenic 5-bit flash ADC circuit diagram and

(b) post-layout simulation results to visualize the high- speed rail-to-rail operation at T = 1 K.

Temperature-dependent static and dynamic power

consumption and (c) the validation of the IDDQ current of the 4 Kb cryogenic SRAM circuit.

In the meantime, such a Cryo-CMOS model-assisted

strategy proves to be effective for the cryogenic analog-to- digital converter (ADC) circuit design (i.e., which serves as the key element to translate the analog readout signals from the quits to the digitalized ones). Here, since the threshold voltage invariably increases by around 0.2 V at low

Fig. 1 (a) Cryogenic 8-bit current steering DAC with an on-

temperatures (Fig. 3), the conventional strong ARM- chip self-biased current reference module. (b) The DNL/INL structure of the dynamic comparator module in room- and temperature-dependent Iref results validate the circuit temperature (RT)-ADC design fails to follow the bit switch performance. Data were re-captured from . when the bias level of the input differential pair is below 0.5

Additionally, this generic platform also enables the design of

challenge, we have re-designed the dynamic comparator unit the cryogenic 8-bit current steering digital-to-analog converter by introducing an additional pre-amplifier stage to enlarge (DAC) which bridges the digital instructions and the quantum the common-mode voltage range and boost the input voltage processor driver. Due to the lack of a reliable Cryo-CMOS swing under the guidance of the cryogenic PDK library. model, previous cryogenic DAC designs had to rely on external

Consequently, the resulting 5-bit flash Cryo-ADC circuit can

current references at room temperature, which inevitably operate in a rail-to-rail mode at T = 1 K with the sampling introduced temperature variation-related errors and noises . rate of 5 MSa/s, as highlighted by the real-time waveforms

Alternatively, we have developed an on-chip self-biased current

in Fig. 18. reference structure in which an additional inverter-type start-up

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