Enquire Now
Home/ ECE & VLSI Projects/ ngspice Simulation Projects
🔲 CMOS & Inverter ⚡ Op-Amp & Amplifier 〰️ Filter Design 🌀 Oscillators & PLL 🔋 Power Electronics 📡 RF & LNA 💡 Digital SPICE 🔷 SKY130 PDK
60+ IEEE 2026 ngspice Topics · SKY130 PDK · Xschem · LTspice · SPICE Netlist · Bangalore

ngspice Simulation Projects
for MTech, BE & PhD 2026

From CMOS Inverter DC and Transient Analysis and Two-Stage Op-Amp Design to Active Filter Synthesis, Ring Oscillator and PLL, Power Electronics (Buck/Boost Converter), Low-Noise Amplifier for RF, 6T SRAM Static Noise Margin, Bandgap Reference, Monte Carlo Mismatch and Noise Analysis — explore 60+ IEEE 2026 ngspice simulation project topics using ngspice, Xschem, Magic VLSI, SkyWater SKY130 PDK, LTspice and Python. Each project includes IEEE base paper, complete SPICE netlist (.cir), circuit schematic, AC / DC / Transient plots, university-format report, PPT and expert viva Q&A for MTech and PhD ECE / VLSI scholars at VTU, Anna University, JNTU and autonomous colleges.

★★★★★ 4.9 / 5 from 418 student ratings
Browse 60+ ngspice Topics Talk to a Mentor
60+
ngspice Topics 2026
9,800+
Scholars Guided
98%
On-Time Delivery

ngspice Simulation Project Topics for MTech & BE — 2026

ngspice is the gold-standard open-source SPICE circuit simulator, implementing Berkeley SPICE3f5 with extensions for modern MOSFET model cards (BSIM3v3, BSIM4, PSP, BSIM-CMG) and open PDKs. It is the primary simulation engine in the open-source IC design flow: Xschem (schematic) → ngspice (simulation) → Magic VLSI (layout) → OpenRCX (parasitic extraction) → ngspice (post-layout) — all on the SkyWater SKY130 130 nm open PDK.

ngspice supports DC operating point (.op), DC sweep (.dc), Transient (.tran), AC small-signal (.ac), Noise (.noise), Monte Carlo (.mc), Sensitivity (.sens), Fourier (.four) and S-Parameter analyses. Projects range from single-transistor biasing to full PLL or ADC behavioural simulation — all grounded in IEEE 2026 journal papers from IEEE TCAS-I/II, IEEE JSSC, IEEE Access and DATE/CICC proceedings.

ngspice Project Specialisations We Cover

  • CMOS Inverter — DC transfer, switching, propagation delay
  • Two-Stage Miller Op-Amp — Gain, GBW, Phase Margin
  • Folded-Cascode OTA — AC analysis, CMRR, PSRR
  • Active Filters — LPF, HPF, BPF, Butterworth, Chebyshev
  • Ring Oscillator — frequency vs VDD, temperature sweep
  • LC and VCO Oscillator — phase noise, spectrum
  • Phase-Locked Loop (PLL) — lock time, jitter simulation
  • Buck and Boost DC-DC Converter — efficiency, ripple
  • Low-Noise Amplifier (LNA) — NF, S-parameters, IIP3
  • Current Mirror and Cascode Bias Circuits
  • Bandgap Voltage Reference — temperature coefficient
  • 6T SRAM Cell — SNM butterfly curve, read/write
  • Monte Carlo mismatch and process corner analysis
  • Post-layout parasitic extraction and re-simulation
🔲

CMOS Circuits

Inverter, NAND, NOR, Transmission Gate — DC, Transient, power analysis.

⚡

Op-Amp Design

Miller two-stage, folded-cascode, rail-to-rail — Gain, GBW, phase margin.

〰️

Filter Synthesis

Active RC, switched-capacitor, Gm-C filters — Butterworth, Chebyshev, Bessel.

🌀

Oscillators & PLL

Ring, Colpitts, Hartley, VCO, PLL — frequency, phase noise, lock time.

🔋

Power Electronics

Buck, Boost, Flyback converter — switching transient, efficiency, ripple.

📡

RF & LNA

Low-noise amplifier, mixer, differential pair — S-params, NF, IIP3.

Tools & Open-Source EDA Platforms

Complete open-source EDA toolchain for ngspice-based analog IC design and simulation — from schematic capture to post-layout verification on the SKY130 PDK.

ngspice 40+ (SPICE Engine) Xschem (Schematic Capture) Magic VLSI (Layout / DRC) SkyWater SKY130 PDK LTspice XVII (Comparison) OpenRCX (Parasitic Extraction) KLayout (GDS / LVS) Python (matplotlib · numpy) MATLAB (Filter Design Toolbox) GNU Octave (SPICE post-proc) HSPICE (Industry Comparison) KiCad EeSchema

Sample Simulation Circuit — CMOS Inverter

Schematic of a CMOS inverter using SkyWater SKY130 PDK NMOS (sky130_fd_pr__nfet_01v8) and PMOS (sky130_fd_pr__pfet_01v8) transistors — the fundamental building block for DC transfer, transient, power and delay analysis in ngspice.

CMOS Inverter — SKY130 PDK (ngspice)

Wn = 1 µm / L = 0.15 µm · Wp = 2 µm / L = 0.15 µm · VDD = 1.8 V
VDD (1.8V) PMOS M1 Vout CL 10 fF NMOS M2 Vin Pulse GND VIN Pulse 0→1.8V .tran .dc .op .meas CMOS Inverter — SKY130 130nm ngspice Simulation

Circuit Components & Parameters

  • M1 (PMOS) — sky130_fd_pr__pfet_01v8, W=2µm, L=0.15µm
  • M2 (NMOS) — sky130_fd_pr__nfet_01v8, W=1µm, L=0.15µm
  • VDD = 1.8 V (nominal), sweep 1.5 V–1.9 V
  • Vin = Pulse source 0 → 1.8 V, rise/fall = 10 ps, period = 2 ns
  • CL = 10 fF (load capacitance)
  • .tran analysis: 0 to 10 ns, step 10 ps
  • .dc Vin 0 1.8 0.01 — DC transfer curve, VM = 0.9 V
  • Measure: tpHL, tpLH, power dissipation, noise margin
  • SKY130 BSIM4 model cards from tt corner
  • Temperature sweep: −40 °C to 125 °C

ngspice Netlist Code — CMOS Inverter (SKY130)

Complete SPICE netlist (.cir) for the CMOS inverter using SkyWater SKY130 PDK model cards — ready to run in ngspice. Includes DC, Transient and measurement commands.

cmos_inverter_sky130.cir  —  ngspice Netlist 
* ─────────────────────────────────────────────────────────────────────
* CMOS Inverter Simulation — SkyWater SKY130 PDK (130 nm CMOS)
* File   : cmos_inverter_sky130.cir
* Tool   : ngspice 40+ | PDK: sky130A | ProjectsatBangalore 2026
* Analyses: DC Transfer (.dc), Transient (.tran), Operating Point (.op)
* ─────────────────────────────────────────────────────────────────────

.title CMOS Inverter — SKY130 ngspice Simulation

* ── 1. Include SKY130 PDK SPICE model library (tt process corner) ──
.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt

* ── 2. Supply and Ground ──
VDD  vdd  gnd  DC 1.8             $ VDD = 1.8 V nominal
VGND gnd  0    DC 0

* ── 3. Input source: Pulse for transient, swept for DC transfer ──
VIN  vin  gnd  PULSE(0 1.8 0.5n 10p 10p 1n 2n)
*                 (V_low V_high Td Tr Tf Pw Period)

* ── 4. PMOS transistor M1 (sky130_fd_pr__pfet_01v8) ──
XM1  vout  vin  vdd  vdd  sky130_fd_pr__pfet_01v8
+     W=2.0e-6 L=1.5e-7 nf=1   $ W=2µm, L=0.15µm

* ── 5. NMOS transistor M2 (sky130_fd_pr__nfet_01v8) ──
XM2  vout  vin  gnd  gnd  sky130_fd_pr__nfet_01v8
+     W=1.0e-6 L=1.5e-7 nf=1   $ W=1µm, L=0.15µm

* ── 6. Load capacitance at output ──
CL   vout  gnd  10f              $ CL = 10 fF

* ── 7. DC Transfer Curve (Vin swept 0→1.8V) ──
.dc   VIN 0 1.8 0.001             $ 1 mV steps

* ── 8. Transient Analysis (10 ns window, 10 ps step) ──
.tran 10p 10n                    $ step=10ps, stop=10ns

* ── 9. Operating Point ──
.op

* ── 10. Measurements ──
.meas tran  tpHL  trig v(vin)  val=0.9 fall=1  targ v(vout) val=0.9 fall=1
.meas tran  tpLH  trig v(vin)  val=0.9 rise=1  targ v(vout) val=0.9 rise=1
.meas tran  Pavg  avg  p(VDD)  from=0 to=10n
.meas dc    VM    when v(vout)=v(vin)  $ Switching threshold

* ── 11. Temperature sweep (−40°C to 125°C) ──
.temp 27   $ Default 27°C; change to -40, 0, 85, 125 for corners

* ── 12. Monte Carlo (100 runs) using SKY130 mismatch parameters ──
* .mc 100 dc VIN 0 1.8 0.01   $ Uncomment for MC mismatch sweep

* ── 13. ngspice interactive plot commands ──
.control
  run
  * DC transfer curve
  plot  v(vout) v(vin) vs v(vin)    $ DC transfer char
  * Transient waveforms
  tran  10p 10n
  plot  v(vin) v(vout)               $ Input vs output
  * Print measurements
  print tpHL tpLH Pavg VM
.endc

.end   $ ── End of netlist ──────────────────────────────────────────
ngspice 40+ SKY130 PDK BSIM4 Model DC · Tran · .meas
42 lines · CMOS Inverter · ProjectsatBangalore 2026

60+ Best ngspice Simulation Project Topics — IEEE 2026

Topics sourced from IEEE TCAS-I, IEEE TCAS-II, IEEE JSSC, IEEE Access, DATE, CICC and ESSDERC proceedings (2021–2026). Primary analysis type and tools listed for each project.

# Project Topic Category Tools / Analysis
🔲  CMOS Circuits — Inverter, Logic Gates, Flip-Flops
01CMOS Inverter DC Transfer Characteristics and Noise Margin — SKY130 PDK ngspiceCMOSngspice · SKY130 · .dc · .tran · Xschem
02CMOS NAND2 and NOR2 Gate Propagation Delay vs Fan-Out Analysis — ngspice ParametricCMOSngspice · .tran · .param sweep · Python plot
03CMOS Transmission Gate Multiplexer: Ron vs VGS and Charge Sharing AnalysisCMOSngspice · .dc · SKY130 PDK · Xschem
04Dynamic CMOS Logic (Domino) — Precharge and Evaluate Phase Transient SimulationCMOSngspice · .tran · BSIM4 · LTspice comparison
05D Flip-Flop (Master-Slave CMOS) — Setup/Hold Time and Metastability SimulationDigitalngspice · .tran · .meas setup/hold · SKY130
06Schmitt Trigger CMOS — Hysteresis Width vs VDD and Temperature SweepCMOSngspice · .dc · .temp sweep · Xschem
07CMOS Standard Cell Characterisation — Liberty (.lib) Timing Arc ExtractionCMOSngspice · Python · Liberty file gen
⚡  Op-Amp, OTA & Amplifier Design
08Two-Stage Miller-Compensated Op-Amp — Gain, GBW, Phase Margin AC AnalysisOp-Ampngspice · .ac · .op · Xschem · SKY130
09Folded-Cascode OTA Design — CMRR, PSRR and Slew Rate ngspice SimulationOTAngspice · .ac · .tran · stb analysis
10Rail-to-Rail Input/Output Op-Amp — Common-Mode Range and Output Swing VerificationOp-Ampngspice · .dc · .ac · 180nm SPICE model
11Differential Difference Amplifier (DDA) — CMRR Improvement Technique SimulationOp-Ampngspice · .ac · .dc · BSIM3v3
12Recycling Folded-Cascode OTA — High GBW with Low Power: ngspice vs HSPICEOTAngspice · .ac · Python post-proc · SKY130
13Chopper-Stabilised Amplifier — 1/f Noise Reduction via Chopping ngspice SimNoisengspice · .noise · .tran · chopper model
14Transimpedance Amplifier (TIA) for Optical Receiver — Bandwidth and Noise AnalysisTIAngspice · .ac · .noise · photodiode model
15Current Mirror Accuracy — Cascode, Regulated Cascode, Wilson Mirror ComparisonBiasngspice · .dc · .op · Xschem · SKY130
〰️  Active Filter Design — LPF, HPF, BPF, Notch
16Active Butterworth Low-Pass Filter (4th Order Sallen-Key) — AC Frequency ResponseLPFngspice · .ac · MATLAB filter design · LTspice
17Chebyshev Band-Pass Filter Design and ngspice Verification — 1 kHz Centre FreqBPFngspice · .ac · Python · MATLAB
18Gm-C Continuous-Time Low-Pass Filter — Tuning Range and Linearity SimulationGm-Cngspice · .ac · .dc OTA model · SKY130
19Switched-Capacitor Filter (SC-LPF) Behavioural Simulation Using ngspice VCVSSC-Filterngspice · .tran · sampled-data model
20Twin-T Active Notch Filter for 50 Hz Power Line Interference Rejection — ngspiceNotchngspice · .ac · LTspice comparison
21Universal State-Variable Active Filter — LP/HP/BP Modes — ngspice AC VerificationFilterngspice · .ac · Python Bode plot
🌀  Oscillators, VCO & Phase-Locked Loop
22CMOS Ring Oscillator — Frequency vs VDD and vs Number of Stages — SKY130 ngspiceRing Oscngspice · .tran · .param · SKY130 · Xschem
23LC Colpitts Oscillator — Start-Up Condition, Steady-State Amplitude and FrequencyOscngspice · .tran · .four Fourier analysis
24CMOS Voltage-Controlled Oscillator (VCO) — Kvco, Tuning Range, Phase NoiseVCOngspice · .tran · .ac · phase noise model
25Crystal Oscillator Equivalent Circuit — Load Capacitance Effect on Frequency PullingCrystalngspice · .ac · RLC crystal model
26Integer-N PLL Frequency Synthesiser — Lock Time and Phase Error Transient SimulationPLLngspice · .tran · behavioural PLL model
27Charge-Pump PLL — Spur Suppression and Reference Feed-Through ngspice AnalysisCP-PLLngspice · .tran · charge pump + VCO model
28Relaxation Oscillator Using Current Comparator — Frequency vs TemperatureRelax Oscngspice · .tran · .temp · SKY130
🔋  Power Electronics — DC-DC Converters, Rectifiers
29Synchronous Buck DC-DC Converter — Efficiency, Output Ripple and Load TransientBuck Convngspice · .tran · PWM model · Python efficiency
30Boost Converter with PID Voltage Loop — Closed-Loop Stability and Step ResponseBoost Convngspice · .tran · .ac loop gain · LTspice
31Flyback Converter Simulation — Primary/Secondary Waveforms, Snubber DesignFlybackngspice · .tran · transformer model
32LDO Voltage Regulator — Line Regulation, Load Regulation and PSRR ngspiceLDOngspice · .dc · .ac · .tran · SKY130
33Three-Phase Full-Wave Bridge Rectifier — Ripple Factor and THD AnalysisRectifierngspice · .tran · .four · diode model
34Class-AB Audio Power Amplifier — THD+N, Output Power and Efficiency SimulationAudio Ampngspice · .tran · .four · BJT Ebers-Moll
35Switched-Mode Power Supply (SMPS) EMI Filter Design — Conducted Noise SimulationEMIngspice · .tran · FFT · Python noise spectrum
📡  RF Circuits, LNA & Mixer
36Inductively Degenerated LNA for 2.4 GHz — NF, S11, S21 and IIP3 ngspice SimulationLNAngspice · .ac · .pnoise · S-param · SKY130
37Cascode LNA at 5.8 GHz — Stability Circles and Noise Figure vs FrequencyLNAngspice · .sp S-parameter · BSIM4 RF model
38Gilbert Cell Double-Balanced Mixer — Conversion Gain and Port Isolation AnalysisMixerngspice · .tran · .sp · Gilbert cell model
39CMOS Low-Power LNA Using Current-Reuse Topology — Power vs NF Trade-offLNAngspice · .ac · .noise · 180nm PDK
40On-Chip Spiral Inductor Q-Factor Extraction — EM Simulation + ngspice Co-SimInductorngspice · HFSS EM export · Python
41Voltage-Controlled Attenuator for AGC — Phase and Gain Control ngspice AnalysisAGCngspice · .dc · .ac · SKY130 NMOS model
🌡️  Bandgap Reference, Bias Circuits & Temperature Analysis
42CMOS Bandgap Voltage Reference — Temperature Coefficient and PSRR ngspice SweepBandgapngspice · .dc · .temp · .ac · SKY130
43Sub-Threshold CMOS Voltage Reference — Ultra-Low Power for IoT Sensor NodesReferencengspice · .op · .temp · weak inversion model
44PTAT Current Generator — Proportional-to-Absolute-Temperature Bias SimulationPTATngspice · .temp sweep · .dc · Python plot
45Wide Swing Cascode Current Mirror — Output Compliance and Mismatch AnalysisBiasngspice · .dc · Monte Carlo · SKY130
💾  Memory Circuits, ADC/DAC & Data Converters
466T SRAM Cell Static Noise Margin — Butterfly Curve (Hold, Read, Write) ngspiceSRAMngspice · .dc 2D sweep · butterfly curve · SKY130
478-Bit R-2R DAC Linearity — DNL, INL and Glitch Energy Transient AnalysisDACngspice · .tran · Python DNL/INL calc
48Flash ADC Comparator Offset and Kickback Noise — Pre-Amp + Regenerative LatchADCngspice · .tran · offset Monte Carlo · SKY130
49SAR ADC Charge-Redistribution DAC — Capacitor Mismatch and Settling Time SimSAR-ADCngspice · .tran · .mc mismatch · Python FFT
50Dynamic Comparator (StrongARM Latch) — Metastability and Kickback AnalysisComparatorngspice · .tran · .op · SKY130 · Xschem
📐  Noise Analysis, Monte Carlo & Process Corner Simulation
51Flicker (1/f) and Thermal Noise Analysis of CMOS Op-Amp — Input-Referred NoiseNoisengspice · .noise · Python noise density plot
52Monte Carlo Mismatch Analysis of Differential Pair — Offset Voltage DistributionMonte Carlongspice · .mc · Python histogram · SKY130
53Process Corner Analysis (SS, TT, FF, SF, FS) of CMOS Inverter Delay — ngspiceCornersngspice · .lib corner · Python boxplot
54Phase Noise Simulation of LC-VCO Using Linearised BSIM Model — Leeson's ModelPhase Noisengspice · .pnoise · BSIM4 RF · Python
55Sensitivity Analysis (.sens) of Filter Cutoff Frequency to Component ToleranceSensitivityngspice · .sens · Python Tornado chart
🔷  SkyWater SKY130 PDK Open-Source IC Design Flow
56Full Open-Source Analog Flow: Xschem → ngspice → Magic Layout → OpenRCX → Post-LayoutFull FlowXschem · ngspice · Magic · OpenRCX · KLayout
57SKY130 CMOS Inverter Layout DRC Clean and LVS Verification — ngspice Post-LayoutLayoutMagic VLSI · ngspice · KLayout LVS · DRC
58Pre- vs Post-Layout Simulation of Op-Amp — Parasitic RC Effect on GBW and PMPLSOpenRCX · ngspice · SPEF back-annotation
59SKY130 Current Mirror Layout — Interdigitation and Common-Centroid for MismatchLayoutMagic VLSI · ngspice · Monte Carlo
60Open-Source IC Tapeout via Efabless Caravel — Analog Block Integration and SimulationTapeoutCaravel · ngspice · OpenROAD · Magic
61Electrothermal Simulation of Power MOSFET — Thermal Resistance and SOA ngspiceThermalngspice · coupled thermal model · Python
62Neuromorphic Synapse Circuit (Memristor + CMOS) — Spike and Plasticity SimulationNeuromorphicngspice · memristor SPICE model · Python
63Machine Learning-Aided SPICE Simulation Speedup — Surrogate Model for Op-AmpML-SPICEngspice · Python · scikit-learn · surrogate
64Transient Electrostatic Discharge (ESD) Protection Circuit — Human Body Model SPICEESDngspice · ESD HBM model · SKY130 clamp
65Analog Compute-in-Memory (CiM) Array for AI Inference — SPICE Accuracy AnalysisCiMngspice · 8T SRAM · Python MAC computation

★ All 65 ngspice simulation project topics are sourced from IEEE Transactions on Circuits and Systems I (TCAS-I), IEEE TCAS-II, IEEE Journal of Solid-State Circuits (JSSC), IEEE Access, IEEE Transactions on Power Electronics, DATE, CICC and ESSDERC proceedings (2021–2026). Each project includes the IEEE base paper, complete SPICE netlist (.cir / .sp) with model card references, Xschem schematic, AC / DC / Transient / Noise analysis plots, parametric study, university-format report for VTU / Anna University / JNTU, PPT (20–25 slides) and 50+ viva Q&A specific to the circuit topology and analysis type.

FAQ — ngspice Simulation Projects

ngspice is the open-source implementation of the Berkeley SPICE3f5 circuit simulator — the industry-standard SPICE engine used for analog, mixed-signal and RF circuit design. Unlike commercial simulators (HSPICE, Spectre, Eldo), ngspice is freely available, supports modern MOSFET model cards (BSIM3v3, BSIM4, PSP, BSIM-CMG), integrates natively with the SkyWater SKY130 open PDK, and runs on all platforms (Linux, Windows, macOS). It supports DC operating point (.op), DC sweep (.dc), Transient (.tran), AC small-signal (.ac), Noise (.noise), Monte Carlo, Sensitivity and S-Parameter analyses — making it ideal for comprehensive IEEE 2026 analog IC design projects that can be published on open-source platforms like Efabless.
Xschem — schematic editor that generates SPICE netlists directly compatible with ngspice and connects to the SKY130 PDK symbol library. Magic VLSI — layout editor with built-in DRC, LVS and parasitic extraction for SKY130. OpenRCX — open-source RC parasitic extractor that generates SPEF files for post-layout ngspice simulation. KLayout — GDSII viewer, DRC and LVS verification tool. Python (matplotlib, numpy, scipy) — post-processing ngspice raw output files (.raw), generating Bode plots, histograms for Monte Carlo, THD+N, DNL/INL calculations. MATLAB Filter Design Toolbox — for deriving filter coefficients before Sallen-Key or Gm-C implementation in ngspice. LTspice — used for quick sanity checks and comparison with ngspice results.
Yes — the SkyWater SKY130 130 nm PDK is fully open-source (Apache 2.0 license), released by Google and SkyWater Technology in 2020. It provides BSIM-based SPICE model cards for NMOS (sky130_fd_pr__nfet_01v8), PMOS (sky130_fd_pr__pfet_01v8), resistors, capacitors and ESD cells — all calleable from ngspice via a .lib directive. The full open-source flow is: Xschem schematic → ngspice pre-layout simulation → Magic VLSI layout (DRC clean) → OpenRCX parasitic extraction (SPEF) → ngspice post-layout simulation → KLayout LVS. This flow supports Efabless Caravel SoC tapeout, making it ideal for highly publishable IEEE 2026 projects.
Yes. All ngspice simulation project reports are prepared per MTech ECE / VLSI Design / Microelectronics / Embedded Systems formats for VTU, Anna University, JNTU, RGPV, PES, RV, Manipal, BITS and autonomous colleges. Chapter structure (Introduction, Literature Review, Circuit Theory and Design Equations, ngspice Simulation Methodology, Results and Discussion, Conclusion), simulation screenshots, waveform plots and circuit schematic with component values are included. The netlist code is documented as appendix code listings per university guidelines. IEEE TCAS / JSSC citation style is used throughout.
Typical completion is 7–21 working days. Single-analysis projects (CMOS inverter DC + transient, current mirror, bandgap reference simulation) are ready in 5–10 days. Full analog IC design projects (op-amp with AC, noise, Monte Carlo; filter with MATLAB design + ngspice verification; PLL with lock-time transient) take 10–15 days. Projects including layout (Xschem → Magic → OpenRCX → post-layout ngspice) or full SKY130 tapeout flow take 15–21 days. Express delivery is available. Contact us on WhatsApp at +91 95919 12372 with your circuit specification and submission date.