OpenROAD Projects

LLM-powered agent that generates, debugs and self-corrects OpenROAD Tcl/Python scripts for physical design tasks — inspired by recent ICLAD and DAC work on agentic EDA assistants.

Closed-loop LLM coding agents (AuDoPEDA-style) that propose and apply code changes to OpenROAD engines to reduce wirelength, clock period and power — reproducible experiments on open benchmarks.

Custom retrieval-augmented generation pipeline and ORD-QA style benchmark for answering OpenROAD documentation questions with high accuracy — useful for both research and education.

Multi-agent system that plans, executes and monitors complete OpenROAD / OpenLane runs, automatically adjusting constraints and re-running failed stages for higher success rate.

Integration of machine-learning models for predictive placement, gate sizing and timing recovery inside the OpenROAD flow — targeting measurable PPA gains on open benchmarks.

Fast ML-based IR-drop predictors trained on OpenROAD power and layout data, enabling early power-grid planning and comparison against traditional analysis engines.

Exploration of GPU kernels for partitioning, placement and routing stages within OpenROAD-Research, aiming at large design scalability and contest-level performance.

Systematic hyper-parameter and flow-script tuning of OpenROAD using Bayesian optimisation or reinforcement learning to maximise QoR across multiple designs and PDKs.

Complete OpenLane / OpenROAD physical implementation of a Linux-capable or microcontroller-class RISC-V core on SkyWater 130 nm, including timing closure, DRC/LVS and GDSII generation.

Design and physical implementation of a domain-specific accelerator (TinyML, crypto, DSP) through the full OpenLane flow on Sky130 or GF180, targeting multi-project wafer submission readiness.

Exploration of hierarchical floorplanning, timing constraints on hierarchical ports and multi-block assembly flows using the latest OpenROAD hierarchical capabilities.

Reproducible comparison of area, timing and power between OpenROAD and commercial place-and-route tools on identical open benchmarks, contributing to the open EDA research ecosystem.

Multi-corner, multi-mode implementation of an ultra-low-power IoT microcontroller using OpenROAD, with power-intent (UPF-style) considerations and leakage optimisation on open PDKs.

Design, place-and-route and post-silicon characterisation strategy for physical unclonable functions and true random number generators implemented entirely with the OpenROAD open-source flow.

Physical design of a custom eFPGA architecture using OpenLane / OpenROAD on Sky130, evaluating routing architecture impact on area and performance.

Development of reusable research modules, testbenches or GPU kernels contributed back to the OpenROAD-Research / ORFS-Research ecosystem for the broader IEEE DATC community.