Physical Design in VLSI Project Topics for MTech & BE — 2026
Physical Design (PD) is the back-end phase of the VLSI design flow that converts a synthesised netlist into a manufacturable layout — covering floorplanning, power planning, placement, clock tree synthesis (CTS), routing, parasitic extraction, static timing analysis (STA) and sign-off. Projects at this level are ideal for MTech VLSI dissertations, BE final year projects and PhD research on EDA automation and open-source PD tools.
At ProjectsatBangalore, we support end-to-end IEEE 2026 Physical Design VLSI projects using the complete OpenROAD RTL-to-GDSII flow on the SkyWater SKY130 open PDK — integrating Yosys for synthesis, TritonCTS for clock tree synthesis, OpenRCX for parasitic extraction, OpenSTA for STA, and Vitis HLS for high-level synthesis — with university-format report, RTL code and viva Q&A.
Physical Design VLSI Specialisations We Cover
- RTL-to-GDSII Automated Flow with OpenROAD + SKY130 PDK
- RTL Synthesis and Logic Optimisation using Yosys
- Floorplanning, I/O Planning and Power Ring Design
- Placement — Global and Detailed (RePlAce, OpenDP)
- Clock Tree Synthesis and Skew Minimisation with TritonCTS
- Global and Detailed Routing (FastRoute, TritonRoute)
- Parasitic Extraction using OpenRCX — SPEF Generation
- Static Timing Analysis and Timing Closure with OpenSTA
- Power Grid Analysis — IR Drop and EM Checks
- High-Level Synthesis: C/C++ to RTL using Vitis HLS
- Low-Power Design: Clock Gating, Multi-Vt, Power Gating
- Custom Standard Cell Design with Magic VLSI + ngspice
- DRC, LVS Sign-Off using KLayout and Magic
- Machine Learning for Congestion Prediction and Timing Closure
RTL to GDSII
Full automated back-end flow on OpenROAD with SkyWater SKY130 open PDK.
Synthesis
Yosys RTL synthesis and technology mapping for ASIC and FPGA targets.
CTS
TritonCTS clock tree synthesis — skew, insertion delay and power optimisation.
STA
OpenSTA + OpenRCX timing analysis — setup, hold, CPPR and ECO closure.
Power
IR drop, electromigration and multi-Vt low-power physical design.
HLS
Vitis HLS for algorithm-to-RTL synthesis of DSP, CNN and crypto accelerators.
EDA Tools & Open-Source Platforms
Complete open-source EDA toolchain for Physical Design in VLSI — from RTL synthesis and floorplanning to routing, STA sign-off and custom layout.
OpenROAD (RTL-to-GDSII)
Yosys (RTL Synthesis)
OpenRCX (Parasitic Extraction)
OpenSTA (Static Timing Analysis)
TritonCTS (Clock Tree Synthesis)
Vitis HLS (High-Level Synthesis)
Magic VLSI (Custom Layout / DRC)
KLayout (GDS / LVS)
ngspice (SPICE Simulation)
Icarus Verilog + GTKWave
SkyWater SKY130 PDK
Python / Tcl Scripting
65+ Best Physical Design in VLSI Project Topics — IEEE 2026
Each topic maps to an IEEE or ACM/DAC/ICCAD publication domain. Tools listed are the primary EDA platforms used in the project implementation.
| # | Project Topic | Category | Primary Tools Used |
|---|---|---|---|
| ⚙️ RTL Synthesis & Logic Optimisation (Yosys) | |||
| 01 | Yosys-Based RTL Synthesis and Technology Mapping of RISC-V RV32I Core to SKY130 PDK | RTL | Yosys · ABC · SKY130 PDK · Icarus Verilog |
| 02 | Logic Optimisation of AES-128 Encryption Core Using Yosys: Area vs Timing Trade-off Study | RTL | Yosys · Synth_SKY130 · OpenSTA |
| 03 | Automated RTL Synthesis Pipeline for Parameterised ALU Designs with Yosys and Python | RTL | Yosys · Python automation · GTKWave |
| 04 | Multi-Cycle Path Analysis and Optimisation During Synthesis Using Yosys + OpenSTA | RTL | Yosys · OpenSTA · constraint scripting |
| 05 | Area-Optimised Synthesis of FIR Filter Core for ASIC Using Yosys with Resource Sharing | RTL | Yosys · ABC optimiser · SKY130 |
| 📐 Floorplanning, I/O Planning & Power Planning (OpenROAD) | |||
| 06 | Automated Macro Floorplanning of SoC Using OpenROAD TritonFP with Wirelength Minimisation | Floorplan | OpenROAD · TritonFP · SKY130 PDK |
| 07 | Power Ring and Power Strap Design for Low-IR-Drop in RISC-V Core: OpenROAD PDN Flow | Power | OpenROAD · PDN scripting · Tcl |
| 08 | I/O Pad Placement Optimisation for Signal Integrity in Mixed-Signal VLSI Chip | Floorplan | OpenROAD · I/O Placer · SKY130 |
| 09 | Hierarchical Floorplanning of Multi-Core Processor Block Using OpenROAD Automation Scripts | Floorplan | OpenROAD · Python · Tcl scripting |
| 10 | Effect of Floorplan Aspect Ratio on Routing Congestion and Timing: Parametric OpenROAD Study | Floorplan | OpenROAD · congestion maps · OpenSTA |
| 11 | Decap Cell Insertion Strategies for Power Noise Reduction in Digital VLSI Blocks | Power | OpenROAD · PDN analysis · OpenRCX |
| 📌 Global & Detailed Placement (OpenROAD — RePlAce, OpenDP) | |||
| 12 | Global Placement of 32-bit MIPS Core Using RePlAce within OpenROAD: Density vs Timing | Placement | OpenROAD · RePlAce · OpenSTA |
| 13 | Timing-Driven Detailed Placement with OpenDP: Reducing Hold Violations in ARM Cortex-M0 | Placement | OpenROAD · OpenDP · Resizer |
| 14 | Multi-Bit Flip-Flop (MBFF) Merging for Dynamic Power Reduction in Placed Netlist | Low Power | OpenROAD · MBFF transforms · OpenSTA |
| 15 | Placement-Aware Routing Congestion Prediction Using ML on OpenROAD Intermediate Data | ML-PD | OpenROAD · Python · XGBoost · congestion data |
| 16 | Gate Sizing for Timing Closure After Placement Using OpenROAD Resizer + OpenSTA | Placement | OpenROAD · Resizer · OpenSTA ECO |
| 17 | Comparing Placement Algorithms: RePlAce vs DREAMPlace on Open-Source Benchmark Circuits | Placement | RePlAce · DREAMPlace · ISPD benchmarks |
| 🕐 Clock Tree Synthesis — TritonCTS | |||
| 18 | CTS for 200 MHz RISC-V Core Using TritonCTS: Skew Minimisation and Power Optimisation | CTS | TritonCTS · OpenSTA · SKY130 PDK |
| 19 | Clock Mesh vs H-Tree Topology Comparison for Low-Skew Distribution Using TritonCTS | CTS | TritonCTS · OpenSTA · Python analysis |
| 20 | Multi-Corner CTS Optimisation for PVT Variation Robustness in SKY130 Designs | CTS | TritonCTS · OpenSTA multi-corner · OpenROAD |
| 21 | Clock Gating Integration with TritonCTS for Dynamic Power Reduction in Pipelined ALU | Low Power | TritonCTS · Yosys gating · OpenSTA |
| 22 | Skew Budget Allocation Across Multi-Domain Clock Networks Using TritonCTS Constraints | CTS | TritonCTS · Tcl constraint scripts · OpenSTA |
| 23 | Post-CTS Hold Fixing Strategy Evaluation in OpenROAD: Buffer Insertion vs ECO Placement | CTS | OpenROAD · TritonCTS · OpenSTA hold ECO |
| 🔀 Global & Detailed Routing (FastRoute, TritonRoute) | |||
| 24 | Full-Chip Routing of RISC-V Core Using TritonRoute on SKY130: DRC Clean GDSII Generation | Routing | TritonRoute · FastRoute · KLayout DRC |
| 25 | Congestion-Aware Global Routing with FastRoute — Via Count and Wire Length Minimisation | Routing | FastRoute · OpenROAD · congestion heatmaps |
| 26 | DRC Violation Analysis and Fix Strategy for 130 nm Technology Routing Rules | Routing | TritonRoute · KLayout · Magic DRC |
| 27 | Signal Integrity: Crosstalk-Aware Routing Optimisation in Dense VLSI Interconnects | Routing | OpenROAD · OpenRCX · OpenSTA SI analysis |
| 28 | Antenna Rule Check and Metal Jumper Insertion in Routed Designs on SKY130 | Routing | OpenROAD · Magic · KLayout antenna check |
| ⏱️ Parasitic Extraction — OpenRCX & Static Timing Analysis — OpenSTA | |||
| 29 | SPEF Generation and Parasitic Analysis of RISC-V Core Using OpenRCX on SKY130 Routed Layout | STA | OpenRCX · OpenSTA · SPEF format |
| 30 | Setup and Hold Timing Closure Using OpenSTA: ECO Buffer Insertion and Gate Upsizing | STA | OpenSTA · OpenROAD Resizer · Tcl ECO |
| 31 | Multi-Corner Multi-Mode (MCMM) STA of AES Core Using OpenSTA with MMMC Constraints | STA | OpenSTA · MCMM corners · SDC |
| 32 | Clock Path Pessimism Removal (CPPR) and OCV Derating in OpenSTA Timing Reports | STA | OpenSTA · CPPR analysis · timing reports |
| 33 | Critical Path Delay Reduction Using Retiming and Buffer Insertion with OpenSTA + OpenROAD | STA | OpenROAD · OpenSTA · Tcl retiming |
| 34 | Parasitic RC Extraction Accuracy Comparison: OpenRCX vs SPEF Estimates for SKY130 Wires | STA | OpenRCX · OpenSTA · Python comparison |
| 35 | Sign-Off STA for Memory Controller ASIC: Path-Group Analysis and Worst-Case Reporting | STA | OpenSTA · SDC · OpenRCX · SPEF |
| ⚡ Power Grid Analysis, IR Drop & Power Estimation | |||
| 36 | IR Drop Analysis of Power Grid in OpenROAD PDN for 200 MHz RISC-V Core | Power | OpenROAD · PDN scripting · OpenSTA |
| 37 | Dynamic Power Estimation Using Toggle-Rate VCD Simulation for AES Core in SKY130 | Power | Icarus Verilog · VCD · Yosys power scripts |
| 38 | Electromigration (EM) Aware Wire Width Optimisation in OpenROAD Routing Phase | Power | OpenROAD · EM rules · OpenRCX |
| 39 | Power Gating Design with MTCMOS Header Cells for Standby Current Reduction on SKY130 | Low Power | OpenROAD · SKY130 MTCMOS cells · OpenSTA |
| 40 | Voltage Drop Impact on Setup Timing: Co-Analysis of PDN and STA in OpenROAD | Power | OpenROAD · PDN + OpenSTA co-simulation |
| 🔧 High-Level Synthesis — Vitis HLS | |||
| 41 | CNN Accelerator Synthesis from C++ Using Vitis HLS: Latency vs Area Optimisation on Alveo | HLS | Vitis HLS · Vivado · Xilinx Alveo U50 |
| 42 | AES-256 Encryption Core HLS: Pipelining and Dataflow Optimisation Using Vitis HLS | HLS | Vitis HLS · SDAccel · co-simulation |
| 43 | Matrix Multiplication Accelerator with Loop Tiling in Vitis HLS for FPGA Implementation | HLS | Vitis HLS · Vivado IP · BRAM optimisation |
| 44 | FIR Filter HLS Design: Comparison of Fully Pipelined vs Resource-Shared Implementations | HLS | Vitis HLS · ModelSim · Vivado |
| 45 | LDPC Decoder Synthesis Using Vitis HLS with Iterative Belief Propagation — Throughput Study | HLS | Vitis HLS · C++ testbench · RTL co-sim |
| 46 | JPEG Compression Pipeline: High-Level Synthesis and FPGA Verification via Vitis HLS | HLS | Vitis HLS · Vivado · AXI streaming |
| 47 | Real-Time Object Detection HLS Accelerator (Tiny-YOLOv3) Deployed on Xilinx ZCU104 | HLS | Vitis AI · Vitis HLS · DPU on ZCU104 |
| 🔋 Low Power Physical Design Techniques | |||
| 48 | Multi-Threshold CMOS (Multi-Vt) Cell Assignment for Leakage Reduction in OpenROAD PD Flow | Low Power | OpenROAD · Multi-Vt scripts · OpenSTA leakage |
| 49 | Clock Gating Insertion in RTL Using Yosys for Activity-Based Dynamic Power Reduction | Low Power | Yosys · ICG cells · Icarus + VCD |
| 50 | Operand Isolation Technique for Low Power ALU Design at RTL and Gate Level | Low Power | Yosys · Verilog · OpenSTA · power report |
| 51 | Fine-Grain Power Gating of Unused Functional Blocks in IoT SoC on SKY130 PDK | Low Power | OpenROAD · SKY130 cells · PDN |
| 52 | Dynamic Voltage and Frequency Scaling (DVFS) Modelling for Energy-Efficient ASIC Design | Low Power | Python · OpenSTA timing corners · analytical model |
| 🎨 Custom Standard Cell Layout — Magic VLSI & ngspice | |||
| 53 | Custom CMOS Inverter Layout in SKY130: DRC and LVS Clean Design Using Magic VLSI | Custom | Magic VLSI · ngspice · SKY130 DRC rules |
| 54 | Standard Cell Library Design: NAND2, NOR2, DFF Cells — Layout, Extract, SPICE Verification | Custom | Magic VLSI · ngspice · xschem |
| 55 | SRAM 6T Bit-Cell Layout and Read/Write Static Noise Margin Simulation in SKY130 | Custom | Magic VLSI · ngspice · SPICE deck |
| 56 | Ring Oscillator Design and Propagation Delay Characterisation in 130 nm CMOS | Custom | Magic VLSI · ngspice · frequency extraction |
| 57 | Custom Comparator Layout for ADC Front-End in SKY130: SPICE Characterisation and DRC | Custom | xschem · Magic VLSI · ngspice |
| 🤖 Machine Learning for Physical Design Automation | |||
| 58 | ML-Based Routability Prediction from Placement Data Using GNN on OpenROAD Benchmarks | ML-PD | OpenROAD · PyTorch Geometric · GNN |
| 59 | Timing Prediction Before Routing Using Random Forest on Post-Placement Netlist Features | ML-PD | OpenROAD · Python · Scikit-learn · OpenSTA |
| 60 | RL-Based Macro Placement for SoC Using Reinforcement Learning on OpenROAD Environment | ML-PD | OpenROAD · PyTorch · PPO RL agent |
| 61 | IR Drop Prediction Map Using CNN on Placed and Routed Power Grid Data | ML-PD | OpenROAD · Python · CNN · PDN data |
| 62 | Congestion Hotspot Detection in Global Routing Using LSTM on OpenROAD Flow Data | ML-PD | FastRoute · Python · LSTM · routing features |
| 🏁 Complete RTL-to-GDSII Tape-Out Projects — OpenROAD + SKY130 | |||
| 63 | Full RTL-to-GDSII Flow for 32-bit RISC-V Processor Core: Yosys → OpenROAD → KLayout Sign-Off | RTL-to-GDS | Yosys · OpenROAD · TritonCTS · OpenRCX · OpenSTA · KLayout |
| 64 | GCD Accelerator Chip Tape-Out on SKY130 via Efabless Caravel Harness Using OpenROAD | RTL-to-GDS | OpenROAD · Caravel · Yosys · Magic DRC · KLayout LVS |
| 65 | SHA-256 Crypto Core Physical Design: Full Automated PD Flow with Timing and Power Sign-Off | RTL-to-GDS | Yosys · OpenROAD · TritonCTS · OpenRCX · OpenSTA · KLayout |
* All 65 Physical Design VLSI project topics are sourced from IEEE Transactions on VLSI Systems, IEEE TCAD, IEEE Access, DAC, ICCAD and DATE proceedings. Every project includes the IEEE base paper, RTL/Verilog source code, OpenROAD / Yosys / Vitis HLS project scripts, university-format report for VTU / Anna University / JNTU, PPT presentation (20–25 slides) and 50+ viva Q&A. SkyWater SKY130 PDK setup guidance is included.
Frequently Asked Questions — Physical Design VLSI Projects
Top IEEE 2026 Physical Design VLSI project topics include: Full RTL-to-GDSII flow for RISC-V core using OpenROAD + SKY130 PDK, Clock Tree Synthesis with TritonCTS for 200 MHz designs, Parasitic extraction and timing closure with OpenRCX and OpenSTA, CNN accelerator HLS using Vitis HLS on Alveo, ML-based congestion prediction, Power grid IR drop analysis, Multi-Vt placement for leakage reduction, and GDS tape-out via Efabless Caravel harness. All include IEEE base paper, RTL code, tool scripts, report and viva support.
OpenROAD — complete RTL-to-GDSII automated PD flow (floorplan, placement, CTS, routing, sign-off). Yosys — open-source RTL synthesis and technology mapping. OpenRCX — parasitic RC extraction to generate SPEF files from routed layouts. OpenSTA — open-source static timing analyser for setup, hold and timing report generation. TritonCTS — clock tree synthesis and skew minimisation engine within OpenROAD. Vitis HLS — Xilinx/AMD tool for C/C++-to-RTL high-level synthesis targeting FPGA and ASIC. Supporting tools: Magic VLSI (custom layout / DRC), KLayout (GDS viewer / LVS), ngspice (SPICE simulation), Icarus Verilog + GTKWave, and SkyWater SKY130 open PDK.
Yes. Every Physical Design VLSI project at ProjectsatBangalore includes the original IEEE Xplore or ACM/DAC/ICCAD/DATE 2026 base paper from journals such as IEEE Transactions on VLSI Systems, IEEE TCAD and IEEE Access. The project implementation reproduces and extends the paper's results — timing reports, layout screenshots and QoR comparisons are included in the project report as side-by-side validation tables.
Yes. All Physical Design VLSI project reports, synopses and presentations are prepared as per VTU, Anna University, JNTU, RGPV, PES, RV, Manipal, BITS and autonomous college formats. Chapter structure (Problem Statement, Literature Review, Methodology, Results, Conclusion), citation style, abstract format and evaluation criteria are customised to your university guidelines on request.
Typical completion timeline is 7–21 working days. Synthesis and STA-only projects (Yosys + OpenSTA) are ready in 5–10 days. Full RTL-to-GDSII flows (OpenROAD + OpenRCX + TritonCTS + KLayout sign-off), Vitis HLS accelerator projects or ML-assisted PD projects take 12–21 days. For urgent deadlines, express delivery is available. Contact us on WhatsApp at +91 95919 12372 with your submission date for a personalised schedule.
VLSI Physical Design Lab — Bangalore
Inside our VLSI Physical Design project development lab — OpenROAD RTL-to-GDSII workstations, Vitis HLS FPGA development setups, Magic VLSI custom layout desks, Yosys synthesis and verification stations, and dedicated research mentoring rooms for BE, MTech and PhD VLSI scholars.
OpenROAD
RTL-to-GDSII
Full Automated PD FlowRTL-to-GDSII
Yosys
RTL Synthesis
Logic OptimisationRTL Synthesis
TritonCTS
Clock Tree
Skew MinimisationClock Tree
OpenRCX
OpenSTA
Parasitic + STA Sign-OffOpenSTA
Vitis HLS
Accelerators
HLS to FPGAAccelerators
Magic VLSI
Custom Layout
DRC / LVS CleanCustom Layout
KLayout
GDS Sign-Off
DRC / Antenna CheckGDS Sign-Off
SKY130 PDK
Tape-Out
Efabless CaravelTape-Out
ML-Aided
PD Research
GNN / RL PlacementPD Research
Report & Viva
Prep
VTU / Anna UniversityPrep