Full-Custom Layout Design Using Cadence — Tools, Boards & Topics
Full-custom analog/digital layout flow in Cadence Virtuoso with DRC/LVS and related topics.
Typical stack includes Verilog/SystemVerilog, ModelSim/Questa, Xilinx Vivado or Cadence Virtuoso, and educational FPGA boards. Packages include sources, testbenches, reports, PPT and viva support.
Tools & Hardware
Cadence VirtuosoAssuraCalibreSpectre
Best Related Project Topics
64+ topics with simulation tools and hardware used.
| # | Project Topic | Tools / Hardware |
|---|---|---|
| Core · Architecture · RTL | ||
| 01 | FULRTL Design of Core Module with Parameterization | Verilog · ModelSim · Vivado |
| 02 | FULPipelined Architecture Variant Study | Verilog · ModelSim · Vivado |
| 03 | FULResource Sharing vs Parallel Implementation | Verilog · ModelSim · Vivado |
| 04 | FULFlag and Status Output Generation | Verilog · ModelSim · Vivado |
| 05 | FULOperand Isolation for Power Reduction | Verilog · ModelSim · Vivado |
| 06 | FULHierarchical Module Partitioning | Verilog · ModelSim · Vivado |
| 07 | FULGenerate-Block Scalable Design | Verilog · ModelSim · Vivado |
| 08 | FULCase vs If-Else Coding Style Comparison | Verilog · ModelSim · Vivado |
| 09 | FULRTL Design of Core Module with Parameterization — Variant 2 | Verilog · ModelSim · Vivado |
| 10 | FULPipelined Architecture Variant Study — Variant 2 | Verilog · ModelSim · Vivado |
| Verification · Testbench · Coverage | ||
| 11 | FULSelf-Checking Testbench with Exhaustive Vectors | ModelSim · SystemVerilog · Coverage |
| 12 | FULConstrained Random Verification Plan | ModelSim · SystemVerilog · Coverage |
| 13 | FULAssertion-Based Property Checks | ModelSim · SystemVerilog · Coverage |
| 14 | FULCoverage-Driven Verification Metrics | ModelSim · SystemVerilog · Coverage |
| 15 | FULGolden Model Comparison (C/Python) vs RTL | ModelSim · SystemVerilog · Coverage |
| 16 | FULWaveform Documentation and Debug Guide | ModelSim · SystemVerilog · Coverage |
| 17 | FULUVM-lite Scoreboard Integration | ModelSim · SystemVerilog · Coverage |
| 18 | FULRegression Suite and CI Scripts | ModelSim · SystemVerilog · Coverage |
| 19 | FULSelf-Checking Testbench with Exhaustive Vectors — Variant 2 | ModelSim · SystemVerilog · Coverage |
| 20 | FULConstrained Random Verification Plan — Variant 2 | ModelSim · SystemVerilog · Coverage |
| FPGA Implementation · Boards | ||
| 21 | FULFPGA Implementation on Basys3 with Switches/LEDs | Vivado · Basys3 / Nexys · XDC |
| 22 | FULDemo on Nexys A7 with 7-Segment Display | Vivado · Basys3 / Nexys · XDC |
| 23 | FULPort to Intel DE10-Lite with HEX Displays | Vivado · Basys3 / Nexys · XDC |
| 24 | FULResource Utilization LUT/FF Study | Vivado · Basys3 / Nexys · XDC |
| 25 | FULTiming Closure Notes for Critical Paths | Vivado · Basys3 / Nexys · XDC |
| 26 | FULConstraint File (XDC/QSF) Best Practices | Vivado · Basys3 / Nexys · XDC |
| 27 | FULOn-Board Self-Test Pattern Generator | Vivado · Basys3 / Nexys · XDC |
| 28 | FULPower Estimation from Vivado Reports | Vivado · Basys3 / Nexys · XDC |
| 29 | FULFPGA Implementation on Basys3 with Switches/LEDs — Variant 2 | Vivado · Basys3 / Nexys · XDC |
| 30 | FULDemo on Nexys A7 with 7-Segment Display — Variant 2 | Vivado · Basys3 / Nexys · XDC |
| Low Power · Coding Styles | ||
| 31 | FULClock Gating Insertion Study | Verilog · ModelSim · Vivado |
| 32 | FULOperand Isolation Techniques | Verilog · ModelSim · Vivado |
| 33 | FULGray Encoding of Control States | Verilog · ModelSim · Vivado |
| 34 | FULPower Report Comparison of Coding Styles | Verilog · ModelSim · Vivado |
| 35 | FULMulti-Voltage / Multi-Mode Awareness | Verilog · ModelSim · Vivado |
| 36 | FULActivity Factor Annotation with SAIF | Verilog · ModelSim · Vivado |
| 37 | FULClock Gating Insertion Study — Variant 2 | Verilog · ModelSim · Vivado |
| 38 | FULOperand Isolation Techniques — Variant 2 | Verilog · ModelSim · Vivado |
| Documentation · Teaching | ||
| 39 | FULLab Manual: Build in 5 Progressive Labs | Reports · PPT · Viva |
| 40 | FULViva Question Bank for the Project | Reports · PPT · Viva |
| 41 | FULTruth-Table to RTL Derivation Pack | Reports · PPT · Viva |
| 42 | FULASIC vs FPGA Resource Comparison Notes | Reports · PPT · Viva |
| 43 | FULStudent Portfolio with Timing/Area Charts | Reports · PPT · Viva |
| 44 | FULCapstone Report Template and Rubric | Reports · PPT · Viva |
| 45 | FULLab Manual: Build in 5 Progressive Labs — Variant 2 | Reports · PPT · Viva |
| 46 | FULViva Question Bank for the Project — Variant 2 | Reports · PPT · Viva |
| Capstone · System Integration | ||
| 47 | FULUART Result Streaming to PC | Verilog · ModelSim · Vivado |
| 48 | FULSPI/I2C Command Interface Control | Verilog · ModelSim · Vivado |
| 49 | FULIntegration into Mini CPU Datapath | Verilog · ModelSim · Vivado |
| 50 | FULCapstone: Full System with Display and Control | Verilog · ModelSim · Vivado |
| 51 | FULMulti-Instance Parallel Compare Logic | Verilog · ModelSim · Vivado |
| 52 | FULUpgrade Path to Wider Bit-Width Design | Verilog · ModelSim · Vivado |
| 53 | FULUART Result Streaming to PC — Variant 2 | Verilog · ModelSim · Vivado |
| 54 | FULSPI/I2C Command Interface Control — Variant 2 | Verilog · ModelSim · Vivado |
| Domain-Specific Extensions | ||
| 55 | FULAnalog Layout Matching | Verilog · ModelSim · Vivado / Cadence |
| 56 | FULCommon-Centroid Techniques | Verilog · ModelSim · Vivado / Cadence |
| 57 | FULGuard Rings and Substrate | Verilog · ModelSim · Vivado / Cadence |
| 58 | FULParasitic Extraction Flow | Verilog · ModelSim · Vivado / Cadence |
| 59 | FULPost-Layout Simulation | Verilog · ModelSim · Vivado / Cadence |
| 60 | FULAntenna and Density Rules | Verilog · ModelSim · Vivado / Cadence |
| 61 | FULExtended Study Topic 61 for Domain | ModelSim · Vivado · Reports |
| 62 | FULExtended Study Topic 62 for Domain | ModelSim · Vivado · Reports |
| 63 | FULExtended Study Topic 63 for Domain | ModelSim · Vivado · Reports |
| 64 | FULExtended Study Topic 64 for Domain | ModelSim · Vivado · Reports |
Contact us for RTL/sources, testbenches, synthesis notes, university-format report, PPT and viva Q&A.
Why Choose Us?
Bangalore guidance for VLSI / FPGA / digital design students.
RTL & Testbench
Clean modules, self-checking testbenches and waveform documentation.
FPGA / Cadence
Board demos, constraints, or schematic/layout flows as applicable.
Timing & Power
Synthesis reports, critical path notes and low-power guidelines.
Report & Viva
University-format documentation, PPT and expected viva questions.
FAQ
Xilinx/AMD Vivado, Intel Quartus, ModelSim/Questa, Cadence Virtuoso where relevant; boards Basys3, Nexys A7, DE10-Lite and similar educational FPGAs.
Yes — RTL/sources, testbench, synthesis notes, report, PPT and viva Q&A.
VLSI / FPGA Lab — Bangalore
RTL, simulation and implementation support.
RTL
Design
Modules · TBDesign
Simulation
Waveforms
ModelSimWaveforms
Vivado / Cadence
Flow
Timing · AreaFlow
FPGA Board
Demo
Basys3 · NexysDemo
Constraints
& Reports
XDC / STA& Reports
Power / Low
Power Notes
ReportsPower Notes
Verification
Coverage
TB · SVACoverage
Viva & Report
Support
DocsSupport