ADC Design using Cadence
ADC Design in Cadence
ADC Design using Cadence(SAR ADC Design) Virtuoso ADE Assembler Using the Virtuoso ADE Assembler, analyze the various conditions of your circuit with an environment that approaches design and analysis from a specification-driven point of view: Quickly test your circuits’ multiple specifications across corners, multiple stimulus testbenches, and statistical variance Added mini-run plans easily create conditional and dependent simulations Built-in advanced statistical features such as worst-case corner development Balance your conflicting design specifications by using advanced optimization technology with SAR ADC Design in Cadence Extensive design checks can be managed in your design to find faulty nets and devices quickly Verify that your assumptions about critical paths in your design are valid by analyzing partial layout and routing parasitics Optional Virtuoso Variation Option for customers needing to do advanced-node statistics (16nm and below), statistical sensitivity, and high-yield estimation of greater than 3 sigma Virtuoso ADE Verifier Get a global view of the circuit status with the Virtuoso ADE Verifier, and easily verify that all the moving pieces of the analog design are contributing to the overall design specifications set by your chip architect. Manual attempts to do this work often lead to mistakes since there is a disconnect between those methods and the design software. This problem does not exist anymore. Now you can: Link analog tests across multiple designers within a company to the highest level specifications of the circuit and view that data in a single, easy-to-use cockpit View test pass/fail results across an entire design team Updates are automatically reflected in the cockpit Use regression testing to build a bridge to the digital world in support of mixed-signal verification Virtuoso Variation Option Use the Virtuoso Variation Option to discover areas where the variance of your design could ruin your results: Simple-to-use, task-driven user interface minimizes set-up time Fast Monte Carlo analysis employs high-performance sampling methods to efficiently verify yield or create corners, with additional speed-up for FinFETs High-yield estimation lets you efficiently analyze the 5- or 6-sigma boundaries of your design One-button click to create worst-case 3-sigma corners Statistically based mismatch and sensitivity analyses