Cadence Genus Synthesis

Abstract—FinFETs are predicted to advance semiconductor design processes. The development of FreePDK15, is thus a

scaling for sub-20nm devices. In order to support their intro- step towards achieving a complete predictive process design. duction into research and universities it is crucial to develop an open source predictive process design kit. This paper discusses In this paper, the development of an entire metal layer stack based on the ITRS estimates has been presented.

in detail the design process for such a kit for 15nm FinFET devices, called the FreePDK15. The kit consists of a layer The standard FinFET layout is evaluated from the point stack with thirteen-metal layers based on hierarchical-scaling of view of fabrication and design rules. Additionally, due used in ASIC architecture, Middle-of-Line local interconnect to limitations of the standard photo-lithography processes, layers and a set of Front-End-of-Line layers. The physical and

geometrical properties of these layers are defined and these state-of-the-art techniques like double-patterning lithography properties determine the density and parasitics of the design. The have been assumed for critical dimensions. Moreover, cut design rules are laid down considering additional guidelines for masks and Middle-of-Line (MOL) layers are facilitated to process variability, challenges involved in FinFET fabrication and enhance cell density and thus require special design rules. To

a unique set of design rules are developed for critical dimensions. validate these design rules, layouts of an Inverter, NAND4,

Layout extraction including modified rules for determining the

geometrical characteristics of FinFET layouts are implemented and their cascaded cells have been designed and their density and discussed to obtain successful Layout Versus Schematic is evaluated. A set of the formulae required to accurately checks for a set of layouts. Moreover, additional parasitic identify and calculate the source and drain dimensions of the components of a standard FinFET device are analyzed and FinFET layout are presented. Additionally, layout extraction

the parasitic extraction of sample layouts is performed. These rules for double patterning, metal stitching and gate cut layers extraction results are then compared and assessed against the validation models. are implemented and validated. The parasitic characteristics of a standard FinFET device are studied and the extraction Index Terms—FreePDK, FinFET 15nm, Process Design Kit, rules for parasitic capacitance and resistance are implemented.

Middle-of-Line layers, DRC, LVS, parasitic extraction.

The extraction of a set of standard layouts is compared and

assessed against first order capacitance and resistance models I. I NTRODUCTION for metal layers.

This paper discusses the intermediate steps involved in the

The International Technology Roadmap for Semiconductors development of process design kit FreePDK15. In section II, (ITRS) forecasts the physical length of the transistors to the layers used for the PDK are discussed. In section III, scale down to 16nm by 20 . However, the scaling of a standard FinFET layout cell is presented and the design bulk MOS technology for sub-20nm transistors has faced rules for these layouts are explained in section IV. Section

major problems - these include high leakage power, random V discusses steps involved in layout extraction. In section VI dopant fluctuations, Drain-Induced-Barrier-Lowering (DIBL) parasitic extraction and validation is discussed and the paper and other short channel effects. An alternative device called is concluded in section VII. a FinFET has emerged, and it has been demonstrated to advance scaling of seminconductor technology beyond 20-nm processes. FinFETs achieve lower sub-threshold leakage and

improved short channel characteristics due to an advanced II. F REE PDK L AYER STACK three dimensional multi-gate geometry. Further, due to an improved gate control and a depleted thin fin structure, they The layer stack for FreePDK is developed considering achieve better short channel performance and have lower multiple factors, including multi-pattern lithography, metal random dopant fluctuation . stitching, dense routing and improvement of contact resis-

The Process design kits (PDKs) for these technologies have tances. The layer stack includes additional layers to ac- already been developed for commercial FinFET processes at commodate for the three-dimensional nature of the FinFET the 1 nm. However, these processes are not readily available device and the layer properties follow the predictions from the for the university education purposes due to the critical nature International Technology Roadmap for Semiconductors 20

of intellectual property. Additionally, a large investment is for the 20 node . required for licensing these processes, which is beyond the The standard cross-section for a FinFET can be seen in scope of universities. Thus, there is an immediate need for Figure 1. The cross-section indicates the use of Middle-Of- development of an open source predictive process design kit Line (MOL) layers along with the standard Back-End-Of-Line to help students gain a detailed understanding of standard (BEOL) layers, and Front-End-Of-Line(FEOL) layers.

it has not been able to achieve the desired yield for volume production. Instead, double patterning is the technique as- sumed for FreePDK15, since it achieves greater pitch density compared to standard single-patterning lithography. This is due to superior contrast obtained from exposed and unexposed areas. In principle, the layout is decomposed into two masks, each with different colors each with half the pattern to be printed. In FreePDK this is implemented by providing two

different colored layers for layers with critical dimensions, like Fig. 1: Cross Section of a FinFET device lower metal layers and gate layer.

For example, in FreePDK15, double patterning is assumed

for gate layers. GATEA and GATEB are two differently

A. BEOL Layers

colored gate layers The ITRS-20 tables for the 20 node predicts use of 1 2) Cut layers: In addition to these layers, FreePDK metal layers. The metal layer stack thus includes 1 layers and also consists of a Gate Cut mask/cut layer called GATEC follows hierarchical scaling used for standard ASIC architec- to remove unwanted features printed by its preceding mask. ture . This is further divided into Metal layer, Intermediate This helps in printing non-uniform device structures and in

metal layers, Semi-Global metal layers and Global metal overcoming errors due to mask misalignment. It is used to layers. break connectivity between gate layers that are continuous.

It is very convenient to form long GATEA/GATEB/GATEAB

shapes and then create multiple individual gate shapes by using a grid of GATEC layers, rather than patterning multiple gate shapes at specific places on the wafer.

As the FinFET device has three-dimensional thin fin

sturcture, it requires additional fabrication steps compared to Fig. 2: MOL layers used as interconnects a standard planar MOSFET. These differences are primarily due to width quantization and use of MOL Layers.

The MOL layers act as an interface between FEOL layers

like ACT and BEOL layers like Metal1. The MOL layers are implemented for overcoming electrical resistance concerns and the loss of performance between inter-connected layers . Al- though the concept of MOL layers has been studied in the past the primary inspiration behind their use for FreePDK comes from . In 14nm bulk FinFET standard cells have been implemented and the impact of MOL layers, local interconnect layers IM and IM2, on cell parasitics is analyzed. MOL layers can be used for connecting internal nets as indicated in Figure

2. Thus these layers help in achieving denser layouts with the

provision for connecting internal nets, internal devices as well as providing connection to the power rails. This eliminates the use of Metal layer for internal routing and thus that of additional contacts/vias.The function of all MOL layers is listed in Table I.

C. Double patterning and other techniques

1) Double patterning: Fabrication beyond 20nm involves multiple challenges, primarily from the standpoint of photo- lithography as the gate pitch is much smaller. It is very difficult to fabricate devices using the standard 193nm Argon Fig. 3: Basic transistor layouts (a) Planar MOS (b) FinFET

Minimum width Defined by the resolution of the lithographic

process used, prevents open-circuits.

B. Advanced design rules

Fig. 4: Dummy gates for process uniformity and DPL These rules are specific to FinFET layout and double patterning lithography.

The layout of a single planar MOS transistor with width W

and gate length L is presented in Fig 3.a. The active layer has a direct contact to Metal layer for the planar MOS. But, in the layout of a FinFET transistor, contact is established through local interconnect layers. Figure 3.b shows the representation of the FinFET layout drawn in the design tool, however, due to the quantization of the fin width the device structure on the physical mask looks different and is illustrated in Fig.3 Fig. 5: Width quantization of the active layer

In order to ensure process uniformity in sub-20nm

transistors “dummy” gates are also printed at the end of the 1) Incremental width rule: Active: The incremental width Fins as seen in Figure 4. Moreover, GATEA and GATEB have rule is introduced due to the discrete nature of the FinFET different patterns for double patterning lithography width. The total width of a FinFET device is defined by the number of fins in the device and thus can only increase in IV. D ESIGN RULE DEVELOPMENT discrete steps. As it can be seen in Figure 5 the active width

The design rules define the basic geometric and connectivity can only increment in steps of 40nm, which is the pitch of the restrictions for a device technology and are thus important active layer . to its development. They ensure sufficient margins against manufacturing process variability. In addition to that they help the designer in verification of the design before it is sent for fabrication. Violations of these rules can result in undesirable operation of the circuits, thus they are critical

to the circuit reliability. Furthermore, these design rules are crucial in defining the density of the integrated circuit as non-optimum design rules would result in wastage of critical design space. Also, with the use of emerging technologies like

FinFETs, it is necessary to introduce new sets of design rules

to efficiently achieve correct functionality.

Typically, the number of design rules can vary from few

hundreds to thousands. The design rules for FreePDK are implemented considering the geometric, electrical and litho-

Fig. 6: Different pitch rules for different layers

graphic constraints. They incorporate standard minimum width and spacing rules, along with certain restrictive design rules. 2) Multi-colored design rules: A distinct feature of device fabrication in the sub-20nm technology is implementation of

A. Standard design rules multi-patterning lithography. In FreePDK double patterning

The standard design rules are listed in Table II lithography (DPL) is assumed. It is thus necessary to use

Fig. 7: Standard inverter cell-FreePDK

different rules for different colored metal layers. Figure 6 Fig. 9: Tiled Inverter layout-FreePDK shows that the required minimum pitch between two similar metal layers, Metal1A layers in this case, is bigger than the minimum required pitch between metal layers of different colors, Metal1A and Metal1B. 3) Restrictive design rules: Restrictive design rules are introduced to maintain the conventional design methodologies with introduction of a new set of restrictions. An example of

restrictive design rule is allowing only discrete gate lengths.

Another example is restriction of jogs and bends in gate

layers as it can result in pinching . However, as this rule causes an increase in the overall area of the layout, it is only implemented for critical dimensions.

The design rules for FreePDK are predictive at best and

need further validation. A set of layouts were drawn and a design rule check was performed on them for validating these rules [?], . 1) Inverter cell: A standard minimum sized FreePDK

Inverter cell is presented in Figure 7. It uses AIL-2 for

connecting the internal nets and power rails. Additionally,

Fig. 8: Standard NAND cell-FreePDK

2) NAND cell: A standard NAND cell shown in Figure Fig. 11: Minimum sized inverter for 45nm bulk CMOS tech-

8 consists of double colored metal layer for layout density; nology(FreePDK45)

the design rules were further validated by running design rule checks.

3) Tiled cells: Tiled Inverter and NAND layouts presented 2) Source and Drain dimensions: FinFET: For bulk Fin- in Figure 9 and Figure 1 resp. are also designed for validating FET devices, the drain and source area is represented by the design rules of higher order metal layers. ADEJ, and ASEJ respectively, while the perimeter of the drain 4) Layout density comparison: The area of minimum sized and source is represented by PDEJ, and PSEJ. The formulae

FinFET inverter is compared with the standard bulk MOS for these parameters account for the number of fins and are inverter designed using 45nm bulk FreePDK pro- as shown in following equations . cess in order to evaluate the layout density of the FinFET process. The layout density in FinFETs does not scale as in ADEJ = ASEJ = nf in ∗ Wf in ∗ Lf in(D/S) (3) bulk MOSFETs. In the layout density for a FinFET design is found to be 1.3 times that for the bulk process at the same

process node of 65nm. The primary reason for this can be P DEJ = P SEJ = 2 ∗ Lf in(D/S) ∗ nf in + Wf in ∗ nf in (4) attributed to the area overhead and width quantization issue in

In order to accurately extract a layout, a layout vs schematic

as shown in Figure 1 was compared with the FeePDK (LVS) rule file is defined. Its accuracy depends on the accuracy

Inverter. The area shrink factor of 45nm CMOS inverter to

of the rule file with regards to device definition and extraction, 15nm FinFET inverter was found to be around 1/6. and connectivity extraction. These rules are validated by creating sample layouts and performing LVS checks on sample V. L AYOUT EXTRACTION AND D EVICE RECOGNITION layouts. A crucial element in the development of the process design FreePDK primarily follows the same LVS rules as defined kit is error-free layout extraction. Layout extraction involves for bulk MOS technology, however, due to the definition of

both device recognition and connectivity extraction, and its MOL layers and introduction of cut-layers some of these rules output is a netlist that contains connectivity information are modified. of all the recognized devices. Thus, layout extraction rules for FreePDK have been developed for transistor devices C. MOL connectivity rules

Due to the introduction of the MOL layers the device

defined yet . contact rules are modified. As indicated in section II-B AIL acts as the first local interconnect to active while GIL acts as A. Device recognition: Bulk MOS vs FinFET the first local interconnect to Gate. However, AIL can act as The shift from traditional bulk planar CMOS devices to local interconnect layer to AIL as well as GIL. This provides FinFETs cause problems in device recognition. In contrast to multiple device contact options: AIL - AIL - M1, GIL -M

the planar devices, FinFETs have a three dimensional folding or GIL - AIL - M1. of gate layer over the fin which adds to the complexity of creating layouts. However, as indicated in section III, the D. Gate Cut rules layout of a FinFET device is drawn similar to planar devices Gate cut layer act as a negative mask and additional rules with a few exceptions. The comparison of a standard NMOS are defined to identify break in connectivity if a gate cut

layout in FreePDK and an NFinFET in FreePDK is shown (GATEC) layer is present. As shown in Figure 13, use of in Figure 12. However, this doesn’t account for the multi-fin GATEC facilitates denser layouts in case of four tiled inverters nature of the FinFETs which results in modification of the by breaking GATE connectivity where required. formulae used for calculating source and drain dimensions of the FinFET device. Additionally, the gate length is only

E. Double patterning rules

restricted to 14, 1 and 2 nm. In most cases a single length of 16nm would be enforced, but it is possible that the critical BEOL rules concern the way in which metal layers are dimensions of all devices may be lengthened to 2 nm or connected. The connection of various metal layers is through shortened to 1 nm across the entire wafer. the alternating via layers, as can be seen in the metal layer It is also very important to correctly extract the drain and stack. For multiple patterned layers, all layers at the same

source dimensions i.e. the area, and perimeter, as they define level in the hierarchy, even with different colors, are treated the parasitic source and drain capacitances. as identical for layout extraction and can be connected to 1) Source and Drain dimensions: Planar MOS: The formu- any of the multiple patterned layers of higher or lower levels lae used for estimating the areas (AD , AS ) and the perimeters of the hierarchy using the corresponding via. For example,

(PD , PS ) of source and drain for planar devices from are intermediate metal layer MINT3, MINT3A, MINT3B are given below. considered same and either of them can be connected to either of MINT4, MINT4A or MINT4B using via VINT3. AD = AS = W ∗ LD/S (1) Similarly, they can be connected to either of MINT2, MINT2A or MINT2B using via VINT2. FreePDK has been developed to allow metal stitching, PD = PS = 2 ∗ LD/S + W (2) which is a means to connect multiple patterned layers to

Fig. 12: Comparison of NFinFET and NMOS layout

predictabilty of wire parasitics and possibly increased chances of a manufacturing defect.

Another important component of the process design kit is

the capability to correctly extract the interconnect and device parasitics. Parasitic extraction is an essential step in analyzing the performance of the design and parasitic capacitance and resistance of the layout are essentially defined by the following layer characteristics: 1) Geometrical characteristics: Minimum-drawn widths, spacing and layer thickness, via enclosures, and trape- zoidal shapes for layers. 2) Electrical properties: Resistivities (or sheet resistances), permittivities for various dielectric layers (dielectric con-

stants), via and contact resistances.

For FreePDK15, the layer definitions and the characteristics

are defined in a technology file or .mipt file and the Mentor

Grpahics’ Calibre xCalibrate and Calibre xRC tools are uti-

lized for parasitic extraction.

A. Layer properties

each other in order to save area. For example, MINT can The values for widths and pitches for various metal layers connect to both MINT5A and MINT5B and vice versa. In were derived from the Interconnect tables from ITRS 20 situations where there are multiple violations to design rules, predictions for the 20 node . However, ITRS-20 pre- specifically spacing rules, instead of modifying the layout to dictions are more aggressive for metal and intermediate metal

increase the area, multiple patterned layers can be used to layer scaling than existing 1 nm processes . Therefore, the color different nets and wherever required metal stitching can minimum width for the metal layer, which is often assumed be used to short two colors (two nets). This is illustrated in to be roughly 1.5 times the minimum gate length, is assumed

Figure 14. The metal stitched layout in figure 14(b) permits to be 2 nm, which is twice that of the minimum gate length.

a smaller spacing between the ZN, VDD, and VDD 2 nets Similarly, the dimensions of the intermediate metal layers are than would be possible if the ZN net were drawn with one based on this assumption, while the semi-global and global color. The downside of metal-stitching, however, is reduced layer dimensions are derived from the ITRS-20 tables. The

(a) Spacing violations between VDD and VDD 2 preventing(b) Metal stitching permitting denser layouts due to use of denser layouts different color of VDD, ZN and VDD 2 nets

Fig. 14: Metal stitching resolves spacing violations and facilitates denser layouts

electrical and geometrical characteristics of the layer stack are dielectric as AIL i.e. SiO and bottom has the same dielectric listed in Table III and TableIV. This stack was chosen to follow as AIL i.e. SiN. while filling in the gaps with materials that provide the The appropriate identification of the metal stack is validated approximate resistivity and dielectric constants predicted by by the output of the XCalibrate’s stack-viewer tool shown in

The modeling of internal parasitics is highly complex due

to the three-dimensional nature of the FinFET structure. How- ever, the BSIM-CMG (for common multi-gate devices) spice model developed by the BSIM group at UC Berkeley accounts for most of the internal device capacitances. How- ever, the fin rises above the substrate resulting in additional capacitance with the external layers.

Figure 1 illustrates various capacitances associated with

a FinFET device. As indicated in Table V, internal device capacitances like Csd , Cgc top are accounted for in the BSIM-

CMG spice model. The other capacitances like contact-

to-contact, gate to contact, and gate-to-substrate are accurately extracted through parasitic extraction process.

The comparison of this model with the FreePDK shows

that the capacitances Cgf top , Cf , Ccc and Cgct are extracted by Therefore, Tetraethyl Orthosilicate (TEOS) is selected as the the rules developed for FreePDK15. The capacitance Cgf top is dielectric surrounding the metal layers, while Silicon Nitride the fringing capacitance for gate over fins, Cf is the capac- (SiN) is selected as the dielectric surrounding all the FEOL and itance between GATE/GIL and AIL1. Cgct and Ccc are again MOL Layers, with the exception of AIL which uses silicon GIL to AIL and GIL to M (in case of a direct connection)

dioxide SiO . Additionally, the top of GIL layer has same respectively. In FinFET layouts, fins are not represented as thin strips, however, the width of the active area is defined as the sum of fin width, and fin pitch times number of fins as

W = W fin + (nfin − 1) ∗ P itchfin (5)

Thus, due to the way in which the width is defined, capacitance Cg is not currently modeled in FreePDK15. Ad- ditionally, these extracted capacitances have not been validated as that can only be achieved by comparing these results against

Thus, the current kit only represents an approximate value of

the extracted FinFET capacitances.

(a) Intermediate metal layers and layer M (b) Semi-Global metal layers (c) Global metal layers

Fig. 16: FEOL and MOL layer stacks in Mentor Graphics’ Stack Viewer

(a) Cross-section view FinFET capacitance

(b) Top view FinFET capaciitance

C. Validation of parasitic extraction The delay analysis was performed for nine-stage FO and

The parasitic extraction process involves capacitive and FO Inverters and the average propogation delay for each resistive extraction of a given layout. The validation process single stage was calculated. Also, the technology models includes design of simple layout and the comparison of their used for the HSPICE simulations were PTMs 1 nm High parasitics with first order models and approximations. Capac- Performance nfet and pfet models , which are based on

itance validations include validation of parallel plate capac- the BSIM models for common multi-gate devices . itance, fringing capacitance and coupling capacitance, while In order to study the impact of additional parasitics on these resistance validation includes comparison of sheet resistance. models the following the propagation delay was computed for 1) Parallel plate approximation: Capacitance between each of the following cases combination of metal layers of varying dimensions are com- 1) Basic circuit based on only the spice models

pared against their parallel plate approximation model. It is 2) Circuit with source and drain dimensions defined. This found that for larger dimensions extracted capacitance for enables inclusion of parasitic capacitance in the spice these metal layers matches the parallel plate capacitance. model. However, for smaller dimensions, (1um*1um) the difference 3) Circuit with extracted parasitic netlist for the corre- between the extracted value and the estimated value was sponding circuit layout.

as high as 100%. This difference is due to the fringing From the delay analysis performed for these cases, it is capacitance which is not included in the parallel plate model, found that the addition of spice model parasitics as well and starts dominating at lower dimensions. as inclusion of the parasitic extraction results increases the 2) Fringing capacitance modification: In order to account propagation delay of the circuit. This is in agreement with

for the Fringing capacitance, the parasitic capacitances are the estimated behavior of the circuit. Furthermore, another compared against the total capacitance values obtained from objective of the delay analysis is to evaluate whether the Sakurai’s and Chang’s approximation. It is found that results obtained from the simulations have the same order of the estimated parasitics have a significantly lower variation magnitude and are within the neighborhood of the propagation

(<10%) even for lower dimensions. delay predicted by ITRS. The simulation result for FO 3) Inclusion of coupling capacitance: Coupling capaci- Inverter is 1.8 ps, while that predicted by ITRS is 3 ps. tance also significantly contributes to the overall parasitic Similarly, the result obtained for FO Inverter is 4.3 ps, while capacitance of the layout, and thus in order to thoroughly that predicted by ITRS is 7.1 ps . This indicates that results

validate it, the total extracted capacitance must be compared are close to the predicted values. with the model that accounts for the coupling capacitance. The process of validation thus involves modifying the dimensions

VII. C ONCLUSIONS

and spacing between the metal layers and comparing that against Sakurai’s approximation. It is found that the difference The introduction of integrated circuit design using Fin- significantly improves (<2%) and remains the same even when FET devices in university education is currently constrained separation or lengths are modified. due to high licensing cost of the commercial design flows. 4) Resistance validation: Simple sheet resistance formula FreePDK attempts to remove this constraints by provid-

was used to validate resistance extraction. The process involves ing an open source predictive process design flow platform varying the lengths and widths of different metal layer shapes wherein circuits for 1 nm FinFET devices can be designed and observing their effects on the extractes parasitic resistance. and verified. In this paper, a PDK is described which consists Sheet resistance values were calculated from the layer prop- of a layer stack based on existing FinFET designs and ITRS

erties table and were used to validate the resistance values. predictions. The design rules encompassing special rules for However, in modern chips, the metal layer often is substituted double patterning lithography, gate cut layers and MOL layers for silicides or mixture of metals with varying quantities are implemented. is used, which cannot give a simple value of resistivity. Since the geometrical characteristics of a FinFET layout Moreover, with effects like skin effect at higher frequencies, differ from that of a planar MOSFET, the modifications

resistance varies with distance from surface and hence parasitic required for correctly extracting the source and drain dimen- resistance validation is kept to this simple sanity check. sions (accounting for the number of fins) and FinFET device recognition are executed. Additional rules requiring layout extraction of interconnects because of double patterning and metal stitching are introduced and validated.

FinFET device indicates additional capacitances due to the

folding of gate over channel. However, due to the manner Fig. 18: Chain of FO Inverters in which the current layouts are drawn all the parasitic components have not been accounted for and would require 5) Inverter chain example: To analyze and evaluate the furtherl complex modeling of the 3D gate structure. However, validity of the kit, the propagation delay for a set of circuits the interconnect capacitances and resistances are validated were calculated and the results were compared with the against standard models and are found to be closer to the

estimated propagation delay from ITRS tables. estimated values. The complete design flow is proven by

TABLE VI: Propogation delay for Inverter chains

Circuit tp - PTM a (ps) tp - S/D specifiedb (ps) tp - extractedc (ps)

3 Single stage propagation delay for circuit with layout extracted netlist

running simulations on extracted netlists of FO and FO FreePDK45, “Webpage for FreePDK45,” www.eda.ncsu.edu/wiki/ Inverters and the propagation delay results of these simulations FreePDK45:Contents, 2008.

M. Alioto, “Analysis and evaluation of layout density of FinFET logic

were found within the vicinity of the results predicted by gates,” in Microelectronics (ICM), 20 International Conference on, ITRS-20 tables for 20 node. Dec 2009, pp. 106–109.

ACKNOWLEDGMENT Source Predictive Process Design Kit for 15nm FinFET Devices.”

diploma thesis, North Carolina State University, Raleigh, NC 27695, The authors would like to thank Paul Franzon at NC State July 2015. University. The authors would like to thank Mentor Graphics, J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital integrated circuits: a design perspective, ser. Prentice Hall electronics and since this project would not have been possible without their VLSI series. Pearson Education, 2003. [Online]. Available: https:

generous gift of supporting funds and Calibre licenses. The //books.google.com/books?id= 7daAAAAYAAJ authors would also like to thank Tarek Ramadan, Ahmed BSIM-CMG 108.0.0 Multi-Gate MOSFET Compact Model author = Khandelwal, S. and Duarte, J. and Sriramkumar, V. and Navid, P. and Lu, Hammed Fathy, Omar El-Sewefy, Ahmed El-Kordy, Hend D. and Lin, C-H. Dunga, M. and Yao, S. and Morshed, T. and Niknejad,

Wagieh and the team at Mentor Graphics for development A. and Hu, C, Technical Manua, University of California, Berkeley. of the first set of design rules and their constant support.In BSIM, “Webpage for BSIM-CMG,” http://www-device.eecs.berkeley. edu/bsim/?page=BSIMCMG, 2012. addition, the authors would like to thank and acknowledge L. Collins, “How to design with finFETs,” http://www.techdesignforums. Alexandre Toniolo at Nangate for clarifying the vision of MOL com/practice/technique/how-to-design-with-finfets/, 2013.

layers. We would also like to thank Cadence designsystems for T. Sakurai and K. Tamaru, “Simple formulas for two- and three- dimensional capacitances,” Electron Devices, IEEE Transactions on, use of the virtuoso software and Synopsys Inc.for use of Pycell vol. 30, no. 2, pp. 183–185, Feb 1983. studio. The authors would also like to thanks Vikas Sharma W. Chang, “Analytical ic metal-line capacitance formulas (short pa-

for P-Cells, Vidyanandgouda Patil for design rule fixes and pers),” Microwave Theory and Techniques, IEEE Transactions on, vol. 24, no. 9, pp. 608–611, Sep 1976. Namrata Sampat for help cleaning up the distribution. PTM, “Webpage for PTM,” http://ptm.asu.edu/, 2012.

ITRS, “International Technology Roadmap for Semiconductors tables -

2011,” http://www.itrs.net/Links/2011ITRS/Home2011.htm, 2011.

C. Shin, X. Sun, and T.-J. K. Liu, “Study of Random-Dopant-Fluctuation

(RDF) Effects for the Trigate Bulk MOSFET,” Electron Devices, IEEE Transactions on, vol. 56, no. 7, pp. 1538–1542, July 2009.

ITRSInterconnects, “International Technology Roadmap for Semicon-

ductors report on interconnects - 2011,” http://www.itrs.net/Links/ 2011ITRS/2011Chapters/2011Interconnect.pdf, 2011.

R. Topaloglu, “Design with FinFETs: Design rules, patterns, and vari-

ability,” in Computer-Aided Design (ICCAD), 20 IEEE/ACM Interna- tional Conference on, Nov 2013, pp. 569–571. P. Schuddinck, M. Badaroglu, M. Stucchi, S. Demuynck, A. Hikavyy, M. Garcia-Bardon, A. Mercha, A. Mallik, T. Chiarella, S. Kubicek, R. Athimulam, N. Collaert, N. Horiguchi, I. Debusschere, A. Thean,

L. Altimime, and D. Verkest, “Standard cell level parasitics assessment

in 20nm BPL and 14nm BFF,” in Electron Devices Meeting (IEDM),

T. Dillinger, “Challenges for FinFET Extraction,” in IEEE Electronic

Design Process Symposium,, April 2013.

Process Design Kit for 15nm FinFET Technology,” in Proceedings of

the 20 Symposium on International Symposium on Physical Design, ser. ISPD ’15. N