Register File Design Cadence

Architectures and Machine Learning Algorithms

Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A Rasul, and Mike Shuo-Wei Chen

University of Southern California, Los Angeles, CA 900

{shiyusu, qiaochuz, mhassanp, juzhengl, rrasul, swchen}@usc.edu

Abstract— Analog mixed-signal (AMS) circuit architecture Digitally-Intensive System

e.g., Software-Defined Radio has evolved towards more digital friendly due to technology

Digital Analog

scaling and demand for higher flexibility/reconfigurability. Mean-

while, the design complexity and cost of AMS circuits has DAC substantially increased due to the necessity of optimizing the circuit sizing, layout, and verification of a complex AMS circuit.

On the other hand, machine learning (ML) algorithms have

been under exponential growth over the past decade and actively ADC A exploited by the electronic design automation (EDA) community.

This paper will identify the opportunities and challenges brought Analog-Intensive System

about by this trend and overview several emerging AMS design e.g., AMS Computing methodologies that are enabled by the recent evolution of AMS Fig. 1: Blurring interface of System-on-Chip (SoC) design. circuit architectures and machine learning algorithms. Specif- ically, we will focus on using neural-network-based surrogate models to expedite the circuit design parameter search and the primitive design unit is down to transistor level instead of

layout iterations. Lastly, we will demonstrate the rapid synthesis discrete digital standard cells, the parameter space of analog of several AMS circuit examples from specification to silicon circuits is enormous compared to its digital counterpart, which prototype, with significantly reduced human intervention. demands substantially more iterations to achieve an optimum design. In addition, AMS design phases, including behavior

I. I NTRODUCTION modeling, schematic design and layout, require close guidance

In traditional circuit design, there are clear boundaries by the analog circuit designers, further increasing the design between the digital back-end, analog mixed-signal (AMS) and time. All those factors set a higher barrier for AMS circuit radio frequency (RF) front-end circuits. As we are approaching synthesis. the limits of CMOS technology scaling in terms of device On the other hand, AMS circuit has gradually moved size and power efficiency, improving the performance of con- towards digital-intensive, analog-lite architectures to leverage

ventional AMS circuits becomes incredibly challenging and the benefits of technology scaling maximally and achieve inefficient. Therefore, circuit designers resort to architectural high flexibility and enhanced performance simultaneously. and/or system-level re-thinking. Consequently, co-design and The digital-intensive AMS circuit architectures enable the co-optimization across devices, circuits, and algorithm have possibility of leveraging digital design flow to synthesize

spawned significant number of innovations in interfaces (i.e., complex AMS circuits like data converters, phase-locked AMS) design. Driven by the growing performance and effi- loops, and digital transceivers. Meanwhile, the advancement ciency requirement of communication and computing system, of machine learning (ML) algorithms has been exploding over the boundaries between analog and digital domain are blurring the past decade. Many algorithmic innovations have resulted

(Fig. 1). As a result, AMS circuits, especially data converters, in significantly improved accuracy for various modeling and become crucial to various emerging systems that need to cross classification tasks. between analog and digital domains. In a nutshell, the industry This shift in AMS circuit architecture along with the recent demands AMS circuits across a wide specification range (i.e., advances in ML algorithms has provided a new opportunity performance, power and area). However, the high degrees of for AMS circuit synthesis with high dimensional optimiza-

freedom for optimizing such circuits poses a great challenge tion, despite the aforementioned difficulties for AMS design. to deliver optimized designs within a reasonable time frame. Moreover, a recent move toward open-source circuit design, In addition, the increasing design cost in advanced technology including EDA tools and IPs, can potentially facilitate AMS nodes further necessitates the reduction of time to market , circuit synthesis. In this paper, we will broadly review the

motivating AMS circuit synthesis. emerging architectures and ML algorithms suitable for AMS

However, the complexity for AMS circuit synthesis is circuit synthesis. Several representative synthesis examples

generally higher than digital circuit synthesis. For example, will be provided. Lastly, we will discuss a potential open- constrained by the accuracy requirement of both continuous source design ecosystem enabled by AMS circuit synthesis. amplitude and time, simulations of analog circuits take sig- The rest of this paper is organized as follows. Section II re- nificantly longer than that of digital circuits. Moreover, since views the mostly digital AMS architectures and the associated

ADC ADC ADC

(a) (b) (c) Fig. 2: (a) Digitally-assisted (b) mostly digital and (c) digital-like architectures.

techniques that favor design automation, especially standard area saving. Likewise, proposed a background calibration digital design tools and flows. Next section III discusses the technique based on adaptive filters to compensate for the new opportunities in rapid AMS circuit synthesis enabled nonlinearity of analog circuits in the ADC. More compre- by the deep learning algorithms, focusing on the NN-based hensive calibration techniques have enabled new regime of

surrogate model for circuit parameter search. Design examples high-performance ADCs . Similarly, advanced digital pre- are provided in section IV. Section V describes the vision distortion and noise shaping techniques have been devel- on open-source AMS design, followed by section VI which oped for wideband and high dynamic range digital-to-analog concludes the paper. converters (DACs) –. In addition to the performance

enhancement, the above digital calibrations also reduce the II. D IGITAL -E MPOWERED AMS A RCHITECTURES analog complexity and ease the design automation.

The key motivation of pushing AMS circuits towards more B. Mostly Digital AMS Architectures

digitally-intensive architecture stems from the fact that analog

In parallel, designers have demonstrated mostly-digital ar-

circuits cannot leverage the CMOS technology scaling intrin- chitectures in the direct sampling receiver and DAC- sically as much as the digital circuits, in terms of both circuit based transmitter using high-performance data converters performance and design cost. Due to the limited benefits for superior system flexibility. Such architectures have also offered by the scaling, architecture innovation has been the been broadly explored for various AMS component blocks main driver of AMS circuit/system performance improvement

to leverage the increasing digital signal processing capability and . As the CMOS technology has advanced to 5nm in advanced nodes. One such example is the digital phase- and below, the short-channel transistors continue to favor locked loop (DPLL), which has attracted much attention mostly digital AMS architectures with performance and cost lately –. By pushing the control processing unit into advantages . digital domain completely, DPLL shows impressive robustness

To illustrate the recent evolution of AMS circuits, we

against process, voltage and temperature (PVT) variations and roughly divide the AMS architectures into three categories, as intrinsically allows digital calibration algorithms to improve shown in Fig. 2. Starting around year 2000, applying digital the performance. More importantly, DPLL can be synthesized signal processing techniques to assist or relax the analog using standard digital design flow thanks to its mostly digital circuit design became an active area of research (Fig. 2(a)).

architecture. Fully synthesized DPLLs have demonstrated a

Motivated by circuit designers pushed the performance of

significantly reduced implementation overhead with perfor- data converters and clock, which aimed to replace most analog mance close to that of analog PLLs , . Similarly, digi- signal conditioning by digital signal processing (DSP), making tal low-dropout regulator (DLDO) was proposed for low-noise the system highly flexible (Fig. 2(b)). However, depending on and low-supply voltage applications . Digitally-intensive the application, extremely high-performance data converters dual-rate hybrid DAC was used to achieve high-speed and

and PLLs might diminish the overall system efficiency. In high-resolution simultaneously . Likewise, thanks to its such scenario, keeping some analog conditioning in the system minimum analog complexity among the ADC architectures, while approximating the analog behaviors with digital-like successive approximation register (SAR) topology has been operations can be a promising alternative (Fig. 2(c)). In the widely adopted , . Since SAR ADC performs the rest of this section, we elaborate those three types of AMS

conversion sequentially, the conversion rate inevitably slows architectures in the context of AMS circuit synthesis. down, as shown in the speed and complexity trade-off in

A major challenge in an AMS design is the fundamental

trade-off between the area of the device and its mismatch. C. Digital-like AMS Operations Larger device provides better matching but also leads to higher Another ongoing trend in AMS design is to use digital gates cost and lower speed. As transistors have been scaled down to achieve or approximate the analog functionalities in order to 65nm and smaller, digital signal processing can relax the to advance the circuit performance and reduce the design cost.

matching requirement of analog circuits with decent power- Consider time-based ADC as an example. In recent years, the and area-efficiency. In , digital calibration is used to relax trend to operate time-based ADC above GHz sample rate has the precision requirement of the residue amplifier in a pipeline increased significantly. The ADC usually consists of a voltage- analog-to-digital converter (ADC) for significant power and to-time converter for encoding the voltage information into

Stage 1 Stage 2 Stage N Vin

... Decoder Decoder S/H ADC DAC Res. DAC ... Amp. CLK CLK

Fig. 3: ADC architecture trade-off. Parameters Metrics

Sizing, Gain, BW, Neural Biasing, Power, Network time domain and a time-to-digital converter (TDC) for quan- Load Area

… (NN) …

tizing the time. The TDC is either a delay-line or a voltage- controlled oscillator – and can be implemented by inverters and flip-flops only. Due to the smaller size of the Fig. 4: NN-based surrogate model. digital circuits, fewer routing parasitics are expected in time- based ADCs. Moreover, digital circuits can achieve fast speed in advanced technology nodes without consuming too much • The device dimension is more discrete, yielding less

power. As a result, the delay line based TDCs in and degree of freedom for circuit sizing. have reached up to 5GS/s using a single channel, which • Layout design rule is more complicated and constrained was previously only possible using Flash ADC or excessive and hence harder for manual design. paralleling (i.e., time interleaving), incurring significant area • The device model and the layout parasitic extraction

and power overhead. Along the same line, a design automation are more complex, dramatically increasing the simulation flow for a mostly digital voltage-controlled oscillator (VCO)- time. based delta-sigma ADC has been proposed and demonstrated Consequently, it is extremely costly to design a close-to recently . Custom library and flow were combined with optimal AMS circuit. Therefore, AMS circuit synthesis with

the digital design flow and scaling benefits were shown by reduced design efforts and sufficiently good performance is comparing different processes. Likewise, proposed a highly desirable. complete design automation flow including logic synthesis, AMS synthesis cast a long research history with various ap- placement, and routing schemes for time-domain computing proaches demonstrated in the past decades. The paper focuses

circuits. In similar manner, utilized NAND gates to the model-based methods due to their fast evaluation speed, implement the current digital-to-analog converter (DAC) for a reusability, and low computational cost. In the early days, the current-controlled ring oscillator. A digital-based operational designers coded all the circuit knowledge in a hierarchical amplifier was proposed as well, blurring the boundary fashion and synthesized relatively small circuit blocks

between analog and digital circuits. Furthermore, a synthe- like amplifiers. Geometric programming was also proposed to sized switched-R-MOSFET-C analog filter was demonstrated cast the Op-Amp design into a convex optimization problem using digital standard cells . In addition to these baseband and later utilized for automating the design of analog circuit blocks, and approximated the amplitude- PLL and pipeline ADC . Other surrogate models

varying (i.e., analog) impulse response of an RF filter with such as support vector regression , , neural network a constant amplitude but a time-varying binary (i.e., digital- (NN) , and Gausian process model , have been like) impulse response, such that the frequency responses widely explored for reducing the computational costs and are similar within a certain band of interest. Based on the model preparation overhead. Among the approaches, the NN

specifications, the impulse response of a target filter is first regression outperforms others since it has more tunable hy- designed using standard digital filter design flows, such as the perparameters, enabling accurate modeling of circuits which FDA tool in MATLAB, followed by the time approximation exercise a sophisticated non-linear function , . There- via pulse-width modulation (PWM). In principle, such digital- fore, NN has been deployed in many computer-aided design

like or time approximated AMS circuits favor the digital EDA (CAD) tools. In the rest of this section, we elaborate on the tools , however specialized algorithms may be needed use of NN-based surrogate model for AMS design. , .

A. NN-based Surrogate Model and Parameter Search

III. NN-A SSISTED AMS D ESIGN A surrogate model can replace the SPICE model to avoid To achieve a complete AMS circuit synthesis, one cannot expensive SPICE simulations, especially the post-layout simu- solely rely on the architecture innovation by incorporating lations in advanced technology nodes (Fig. 4). A NN surrogate mostly digital design. New design methodology for AMS model was proposed to characterize the circuit’s metrics in

circuits is essential to tackle the grand challenges posed by , . A single NN model was used to predict the metrics advanced technology nodes (16nm and below), which results of a circuit as simple as a single-stage amplifier or as complex from the following observations: as a PLL . Unfortunately, similar to other regression

x x xN

AMS in

sub- sub- Sub- out in out circuit circuit circuitN Circuit

x=[x1, x2, xN, xR] x x xN xR sub- sub- sub-

ANN ANN ANN

...

... Multi-layer ... 1-layer ... FC-NN FC-NN ... direct path y y sequential path

methods, NN exhibits an increase in regression error when Schematic Model the target circuit is larger. Therefore, the hierarchical design Parameters Metrics

method divides a complex system into smaller sub-circuits Wt, Lt … SFDR called modules and models these modules using regression. Wcap, Lcap Power

With behavioral or functional models, the modules’ metrics … …

are then related to the system specifications. NN herein plays the role of module-level characterization . In contrary, Layout Model

Parameters Metrics

used the NN to model the metrics-to-parameters function of the modules and used the trained model to set the initial Wt, Lt … Trained

Wcap, Lcap Power

parameter values for further optimization using SPICE sim- NN … … ulations. suggested to perform a global search with the genetic algorithm using SPICE simulations at first, then train the NN model using data points in the vicinity of global search Fig. 6: Transfer learning from schematic to layout models. outcome, and finally perform local optimization using the

trained model to further improve the performance. Although, the approach is efficient in enhancing the optimization speed, structure was customized according to the circuit connection. the NN model needs to be trained every time the global The method achieves higher accuracy compared to the conven- optimization is performed and cannot be reused as a result. tional fully-connected network (Fig. 5) given the same number of training data. Alternately, CCI-NN requires less training

In general, conventional hierarchical design fails to model data to achieve the same model accuracy as a fully-connected the system properly when interactions among the modules network. Also, the network only requires a single dataset become more extensive. Precise system modeling requires generated from the system simulations and does not need proper interface characterization, without which interface multiple training dataset for the modules and behavioral or

problem occurs. The module linking graph (MLG) concept functional modeling between modules’ metrics and systems’ first introduced in accommodates a platform where the specifications. CCI-NN can inherently learn the module-to- modules’ interface can be part of the system modeling. MLG system relations and model the interfaces among the modules is a directed graph containing the modules as the vertices better. showed that for proper modeling of an 8-bit 20GS/s

and the direction of the edges shows the cause and effect current-steering DAC, CCI-NN required at least four times relations between two modules. Since estimating system spec- less training data compared to the regression models using ification with MLG requires many iterations, NN modeled conventional fully-connected NN. modules are used in but only for global optimization.

Combining global optimization and sufficiently accurate NN B. Transfer Learning

models accelerates the search process while delivering nearly Despite the promising efficiency and accuracy of the ap- optimal results. After global optimization, proposed to proaches, most works mentioned above only focus on the perform local optimization with SPICE simulations, removing schematic design in a particular technology node without the least significant parameters based on their gradients. The considering PVT variations. To leverage the trained surrogate

algorithm, called MOHSENN, can rapidly synthesize various model when the design conditions are changed, proposed AMS circuits with comparable or even better performance than a transfer learning (TL) technique. Instead of training the NN manual design from an experienced designer. model from scratch with a large number of samples from The idea of MLG was further explored in . Referred the time-consuming post-layout simulations, the TL technique

to as circuit connectivity inspired NN (CCI-NN), the NN starts from an existing schematic-level circuit model, attaches

Human in Loop Automated

(Developer) (User)

Time 1. Break the circuit 6. Verification with 7. Final verification

into Modules MLG and SPICE with SPICE (a)

CNN 2. Make 5. Global search the 8. Local

testbenches regression model optimization Stop

Satisfactory region Time

(b) 3. Build MLG

4. Make dataset and 9. Final

regression model netlist/GDSII

CEPA.

Fig. 8: Proposed design flow based on AMPSE.

one input linear layer and one output linear layer to the trained model, and only trains the new layers with a few post-layout parameter space, which helps to sample the training data for samples. For the first time, efficiently incorporated the the NN-based surrogate model and hence expedite the whole layout parasitic information into the circuit surrogate model. parameter search process.

Proved by experiments, this modeling method can effectively

reduce the required training samples for a layout-level circuit model while maintaining a high modeling accuracy. IV. P ROPOSED D ESIGN F LOW AND E XAMPLES FOR AMS

With this highly-efficient approach, has successfully S YNTHESIS

demonstrated a layout-aware AMS design flow from speci-

A. Analog/Mixed-signal Parameter Search Engine

fication to layout, using an AMS filter as the test vehicle. took one step further and applied TL to train a silicon- Fig. 8 shows the proposed design flow based on an open- level circuit model and design the circuit incorporating both source AMS circuit generator, called Analog/Mixed-Signal layout- and silicon-level information. This way, the NN-based Parameter Search Engine (AMPSE) , . First, AMPSE approach for sophisticated AMS design has been significantly developers select promising circuit architectures from known

enhanced. Details of those design examples will be discussed good designs (KGD), break them into smaller modules, in the next section. and parameterize the modules. Then, the developers make testbenches for characterizing each module and build MLG

C. Verification based on the connection between the modules. After the

SPICE simulation plays an important role in the AMS preparation, modeling and parameter search can be fully circuit synthesis. For example, one would rely on accu- automated without human in the loop. NN serves as the rate simulation results for validating the synthesized circuit. surrogate model to represent the mapping between the design

Unfortunately, AMS circuit simulations, especially transient parameters and performance metrics. The model is trained

simulations, are typically time-consuming because of the with a dataset generated from the SPICE simulation, which inherent complexity of the SPICE models and the required is assisted by CEPA for reduced training efforts. Transfer number of samples for FFT evaluation. To address these learning is applied to incorporate post-layout information for limitations, simulations of unsatisfactory designs can be ter- improving the modeling accuracy. When the surrogate models

minated according to early-stage simulation results, which can of all the modules are prepared, they are used for global potentially save a significant amount of machine computation parameter search by connecting the models using MLG and time. Some physical and empirical formulas can quickly applying gradient-based search algorithms. Thanks to the fast estimate the performance but lack high accuracy of judgment. inference of NN, the search process is accelerated by orders

proposed a convolutional neural network (CNN) based of magnitude compared to the SPICE simulation based global early performance assertion scheme, named CEPA, for fast search. AMPSE also suggests local optimization with SPICE and accurate verification. CEPA takes a short duration of a model to fine-tune the circuit performance. Owing to the transient waveform to predict the satisfaction of the target decent accuracy achieved by the surrogate model, the optimum

specifications, which are typically obtained in the frequency design can be expected near the parameter candidates from domain after long transient simulations. Trained with a few the global search stage. Hence, the local optimization requires samples, the CNN can extract both human-recognizable and only a small number of iterations. For final verification, the -unrecognizable features from the short transient waveform SPICE simulation with the combined netlist is performed in

and use such features for performance prediction. Note that the end. The whole AMPSE flow leverages both designer’s the learned features from the schematic simulations can be knowledge and the recent advancement in machine learning transferred to the post-layout model, with only a small number and optimization, demonstrating highly automated and fast of training data from the post-layout simulation. As an appli- AMS circuit generation with a wide specification range and

cation, CEPA can quickly narrow down the feasible design high performance.

Track & Hold

DAC and DAC 1 Comparator

Number of Bits

Vin 9 Logic

Driver Dout 8

winv winv winv wcinv wck wck wcin

0 1 2 3 4 5 6 7 8 2 Sampling Rate (MS/s) Fig. 11: Number of bits versus sampling rate.

Track and

Comparator wrdy SAR Driver Hold & DAC Logic

mainly consists of eight-channel time-interleaved RF DACs and a TAF pattern control circuits. We synthesized the control noisec dlyRDY dlyDAC

circuits using standard digital design flow and the DACs using pwdrv

a custom mixed-signal layout flow. The custom flow incorpo- Fig. 10: MLG of the SAR ADC. rated the designer’s insights, such as symmetry and dummy constraints, to ensure high performance. A top-level script then integrated the two parts. To derive a nearly optimum filter

B. Example 1: SAR ADC

response for the TAF, the impulse response was first designed In this example, the design was a SAR ADC from . based on the mathematical analysis and then optimized with As shown in Fig. 9, the ADC consists of four modules, i.e., a coordinate descent algorithm. This hybrid approximation

track/hold and DAC, comparator, SAR logic, and a driver. scheme significantly reduced the time approximation errors There were 2 design parameters and 5 design specs. The of TAF over a wide range of filter’s specifications.

objective was to satisfy all the specs while minimizing the power consumption. Fig. 1 shows the MLG of the SAR ADC, D. Example 3: Silicon verified and enhanced VCO design where the shared edges among modules represent the interface In the last design example, we demonstrated a “from specifi-

elements. AMPSE could generate around 5 different design cation to silicon” design of voltage-controlled oscillators . candidates within 7 minutes which satisfied the specs. Fig. 1 After training the schematic-level VCO model, we generated

shows the corresponding ”banana” curve of the SAR ADC the layout samples using the ALIGN layout automation tool obtained by AMPSE. The plot depicts the possibility of the and developed the layout-level model via TL. With

design outcomes for a given numbers of bits and sample the layout-level model, we designed ten different VCOs via rates. For a 6-bit 5 MS/s case, AMPSE reached similar AMPSE, laid out and taped out the silicon chip in the 12nm

performance as global search using the SPICE model while FinFET technology. The fabricated VCOs were measured and achieving almost 7 times faster search speed than the evaluated in terms of oscillation frequency and power con-

simulation-based method. sumption at different control voltages. Compared to the layout- level design results, the silicon measurement results showed

C. Example 2: Delta-Sigma and RF DACs

a 12% mean square variation. We then performed TL to In , we demonstrated the design of delta-sigma DAC tune the model using silicon-level samples (i.e., measurement in 65nm CMOS technology. The capacitor delta-sigma DAC data) and used the updated model to re-design the VCOs.

consists of one inverter-based driver, one capacitor, and as- Thanks to the silicon-level circuit model, the design flow could sociated digital circuits. We first utilized CEPA to rapidly accurately predict the real silicon performance and found the

explore the design parameter space of the DAC and locate corresponding design parameters with a 3.9% mean square the feasible region as the target design space. We then used prediction error.

NN to model the mapping between the design parameters and

the performance metrics within this design space and applied V. O PEN -S OURCE E COSYSTEM FOR AMS D ESIGN TL with post-layout simulation results to improve the model. Moving forward, the growing demands and design cost of

Finally, we applied gradient descent on the NN model to AMS circuits continuously challenge circuit designers and search for the best possible design parameter combinations EDA tool developers. Besides, it is well-known that AMS

given the specifications. The DAC layout was generated using circuit design is a highly specialized research area, where a mixed-signal layout flow . The fully synthesized delta- experienced designers’ knowledge and intuition play a key

sigma DAC achieved a 8 dB SFDR and 8.8-bit ENOB for role in successful designs. The shortage of design expertise 1 MHz signal bandwidth. becomes the bottleneck of the current design capacity of

We have also explored RF-DAC-based AMS filter using the industry. The recent DARPA Posh Open Source Hard- time-approximation filter (TAF) architecture . The filter ware (POSH) program aims for an open-source hardware IP

IP IP

</> PDK TL on tech.

Open-source IP developer Open-source IP user

Fig. 12: Open-source AMS design ecosystem.

ecosystem. The open-source environment is widely adopted ACKNOWLEDGMENT in software and digital design. However, it is still a fresh concept in the AMS circuit community for its technology The work is supported in part by DARPA ERI POSH dependency, IP sensitivity, reliability requirement etc. In Fig. program under Grant FA8650-18-2-78 and in part by Glob- 12, we present a potential AMS circuit design ecosystem alFoundries. The authors would like to thank Prof. Anthony

for sustainable and secure IP sharing, aiming to dramatically F. J. Levi and Prof. Sandeep K. Gupta from the University of increase the AMS design capacity. The open-source AMS Southern California for technical discussions.

IP developers choose the silicon-proven circuit architectures

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