Spice Netlist Cadence

Priyam Kumar, Akshada Khele, Aditee C. Joshi*

ajoshi@unipune.ac.in ; aditee04@gmail.com

The presented paper introduces a design for a demonstrates a lock-in range spanning from

phase-locked loop (PLL) that is utilized in 70.4 MHz to 1 MHz, with an output frequency synthesis and modulation- frequency range of 1.1 GHz to 2.7 GHz. It demodulation within communication systems achieves a lock time of 260.0 ns and consumes and in VLSI applications. The CMOS PLL is a maximum power of 5.1 mW at 2.4 GHz. designed using 1 nm Fabrication Technology Keywords: Phase Locked Loop (PLL), Phase

on Cadence Virtuoso Tool with a supply voltage Frequency Detector (PFD), current starved VCO of 1.8 V. The performance is evaluated through (CSVCO), Charge Pump(CP), Loop Filter(LP). simulations and measurements, which demonstrate its ability to track and lock onto the I. INTRODUCTION

input frequency. Phase locking, a concept introduced in the

The PLL is a frequency synthesizer 1930s, quickly gained significant popularity in

implemented to generate 2.4 GHz frequency. the fields of electronics and communication .

The input reference clock from a crystal Primary goal of the PLL is to achieve

oscillator is 1 MHz square wave. Negative synchronization between the output oscillator

feedback is given by divide-by-1 frequency signal and a reference signal. In the context of a

divider, ensuring the phase and frequency phase difference, the term "leading phase"

synchronization between the divided signal and denotes a wave that occurs before another wave

the reference signal. The design has essential of the same frequency, while the term "lagging

components such as a phase frequency detector, phase" refers to waves that occur after another

charge pump, loop filter, current-starved wave of the same frequency.

voltage-controlled oscillator (CSVCO), and frequency divider. Through their collaborative operation, the system generates an output frequency that is 1 times the input frequency.

The centre frequency of the 3-stage

CSVCO is 3.2 GHz at 9 mV input voltage.

A phase-locked loop reduces phase discrepancy input voltage that is controlled. By varying the

between the output and input frequencies. When applied control voltage, the frequency of the phase difference between these signals oscillation can be adjusted. The control input reaches zero, the system is considered "locked." voltage governs the output frequency of the The PLL achieves this locking behavior through VCO. the utilization of negative feedback. 5. Frequency Divider (FD): Frequency divider

1. Phase Frequency Detector (PFD): By signal. The input signal to the phase detector is

comparing the phase and frequency of the derived from the VCO output, passing through a reference signal with the phase of the feedback frequency divider that scales down the output signal, the PFD generates an error signal that is frequency to match the reference frequency. proportionate to the phase difference.PFD has II. CIRCUIT IMPLEMENTATION two outputs UP and DOWN, which are The design and evaluation of various blocks of

generated according to which input is leading. phase locked loop are explained in the section.

2. Charge Pump: The charge pump takes the A. Phase Frequency Detector:

error signal and produces a current that regulates PFD can be understood from the Fig. 2. and 3 the voltage-controlled oscillator. During the The clock inputs of the flip-flops are linked to high state of the UP signal, a positive current inputs A and B. When initially both QA and QB flows through the circuit, resulting in charging are at a logic low state (QA = QB = 0), if input of capacitor. When the DOWN signal transitions A transitions to a logic high state, the output QA

to a high state, a negative current is induced in will rise accordingly. Similarly, When a rising the circuit, leading to a decrease in the control transition occurs on input B, the subsequent voltage, thus discharging of capacitor. action for another flip-flop is that QB goes high.

3. Loop Filter: This block converts the current NAND and Inverter are combined to form AND

from the charge pump into a voltage signal, gate which is used to resets both the flip flops. which represents the average output of the phase In other words, both QA and QB experience a detector. This voltage signal is then provided as simultaneous peak for a brief duration, the an input to the VCO. This design utilizes a difference in average values between them second-order low-pass filter, which eliminates effectively represents the input phase or

noise and high-frequency components from the frequency difference. charge pump output, which increases stability.

4. Voltage Controlled Oscillator: It is an

electronic device that produces oscillations whose frequency is determined by an applied

Fig. 5 Layout of PFD

Fig. 3 Output of PFD B. Charge Pump along with Loop Filter:

A charge pump circuit comprises a current

source and two inputs from a phase frequency

Each flip flop can be implemented as shown in

detector (PFD) with latches, enabling control Fig. 4 where two RS latches are interconnected over the current flow into and out of the filter. in a cross-coupled manner. Latch 1 is triggered The filter, typically a low-pass filter, is by the rising edges of the CLK signal, while integrated with the charge pump after its Latch 2 responds to the rising edges of the Reset implementation. The design of the filter relies signal . This design has advantage that it on second-order derivatives, and the values of

require less number of transistor and generating resistors and capacitances are determined using the required waveform for phase and frequency these derivatives . Fig. 6 illustrate the circuit, detection. It also overcome dead zone problem where the PFD outputs are connected to the as it has delay element in the reset path which is charge pump circuit containing the current

AND gate . source implementation, and the loop filter is

integrated to the charge pump, with its resistance and capacitances calculated accordingly.

KPDI=Ipump/2*Π(A/radian) (2)

∆Φ=Φin– Φref (3)

Fig. 6 Schematic of CP along with LF

C. Voltage Controlled Oscillator: When the loop is in lock, the phase difference In this work, a voltage-controlled oscillator (∆Φ) becomes zero. The input voltage to the (VCO) based on the current-starved principle is

Vinvco=Kf×IPDI (4) current. By limiting the current flowing through

where Kf represents loop filter gain. Fig. 7 the inverter, it is possible to keep the oscillation displays the simulation result of the Charge frequency constant. The design of the current- Pump output in response to the generation of the starved VCO incorporates a ring oscillator, and

UP signal. its functionality closely resembles that of a

typical ring oscillator.A ring oscillator is formed by cascading an odd number of inverters in a series configuration.The output of the final inverter is connected back to the input of the initial inverter in a feedback configuration.For our design number of inverter stages is fixed with Three. At a supply voltage of 900mV, the Fig. 7 Simulation of PFD and CP along with VCO is designed to achieve a center frequency LF of 3.2 GHz. Fig. 8 displays the layout of the charge pump The Schematic of 3 stage VCO is shown in Fig.

and loop filter integration. The area measured 9 for CP with LF is (34.3 𝜇m* 45.1 𝜇m) 1550.7 𝜇m2.

The M and M2MOSFETs forms an inverter, The performance analysis for the CSVCO for

whereas M and M function as current generating the different frequencies with

sources. The M and M MOSFETs restricts different control voltages are shown below in

the amount of current that can flow to the M the graph in Fig 11.

and M inverter, effectively starving it for The table below shows different parameters of

current. Both M and M MOSFETs have equal CSVCO according to the design configuration.

drain currents, which are determined by the input control voltage. Each stage of the inverter and current source mirrors the currents flowing through M and M8. The gate of M is linked to the upper PMOS transistors, All the low NMOS transistors have their gates connected to the source voltage. The ability to tune the oscillation

Fig. 11. Freq. Vs Vin of CSVCO

frequency over a wide range is a benefit of this

Table I. Design Parameters of CSVCO

configuration, achieved by adjusting the value of

Sr. Parameters Observation

the control voltage,. Moreover, shows no linearized CSVCO by keeping resister in series 1. Technology 180nm with M8. 2. Supply voltage 1.8V 𝑓 −𝑓 3. No. of transistors 1

TSPC Logic

Fig. 12. Layout of CSVCO When clock is zero, at that time if D is 1 then

D. Frequency Divider: M will turned off. Transistor M will be ON

Through the frequency divider circuit, the thus B is 0. So the particular Signal A is output of the VCO is looped back to phase irrespective of the input. At clock 0, A is 1. The frequency detector input. The frequency divider M Transistor is Cut-off. Thus the Q bar value circuit reduces the frequency of the output will be there as it is, as M will also Off. When signal coming from VCO. This circuit is Clock goes high, M will be Off. B remains at

essentially a D flip-flop (DFF) with its output 0. M and M will turned on. As a result A connected back to its input, forming a feedback remains high. Transistor M gets off. And m loop in Fig. 13. A frequency divider with a and m turned on. Thus Q bar signal goes low. division ratio of 1 is employed in this design. Power consumption of Divide by 2 Counter at Four D ffs are cascaded to form divide by 1 different frequencies is given in chart below.

divider. Now there are two kind of FFs which Table II. Power consumption of Divide-by-2 are used for frequency division. TSPC D-ff 1) Strong- ARM latched based flip flops and VCO Counter Power 2) TSPC based flip flops . Output output (𝛍W)

TSPC based FFs has lesser power consumption Frequency Frequency

in general as compared to strong -ARM latched 1 MHz 500.9 kHz 0.2 based FFs. It is also quite fast and as there are 1 MHz 5.0 MHz 2.3 lesser number of transistors it operates at higher 1 MHz 49.9 MHz 9.0 frequency. Thus, TSPC based frequency 1 GHz 500.4 MHz 94.2 division method is used in this design . 2 GHz 1.00 188.8 GHz

Cascading four divide by 2 D-ff will give divide

by 1 frequency divider as depicted below in fig. 1 and 15.

Fig. 1 exhibits the simulation results of the

Fig.1 Schematic of divide by 1 FD PLL in a locked state, operating at reference frequency of 1 MHz.

The PLL circuit is created and tested using the

𝜇m* 45.1 𝜇m) 1550.7 𝜇m as seen in Fig.16. Cadence Virtuoso 180nm CMOS Technology, with a supply voltage of 1.8V.The output frequency of the CSVCO is varying from 1.0

GHz to 3.7 GHz, depending on the input

voltage of the VCO. The PLL consumes a maximum power of 5.1 mW. Currently, the

PLL is functioning correctly and generating an

output frequency of 2.4 GHz. The design of

Fig. 1 Layout of Divide-by-1 Divider

of chip is reduced and also the power

Table III. Simulation Result of PLL

such as PFD, CP, LF, VCO and divide by 1 Parameters Observation divider, It is important to integrate all these Technology 1 nm blocks to form PLL. Following is the schematic Power consumption 5.1 mW

of the PLL in Fig. 17. Lock Time 260.0 ns for 2.4 GHz

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