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🔷 IEEE 2026 · RTL Only · Vivado · QuestaSim · Verilog · SystemVerilog

MTech Projects for VLSI Design

65+ latest RTL-only VLSI Design project topics using Xilinx Vivado and Siemens QuestaSim — Combinational & Sequential logic, FSM, ALU, UART/SPI/I2C, AXI, DSP filters, CPU cores and SystemVerilog verification. Complete packages with IEEE base paper, RTL code, simulation, report, PPT and viva support — Bangalore.

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Combinational Sequential FSM Arithmetic Protocols DSP RTL CPU / Processor Verification

MTech Projects for VLSI Design — RTL Only with Vivado & QuestaSim 2026

All projects on this page are pure RTL (Verilog / SystemVerilog). Design entry, synthesis and implementation use Xilinx Vivado; functional simulation and coverage use Siemens QuestaSim. No analog or mixed-signal topics.

Why choose RTL VLSI projects at ProjectsatBangalore?

  • IEEE / ACM style base papers
  • Complete Verilog / SystemVerilog RTL
  • QuestaSim testbenches & waveforms
  • Vivado project & constraint files
  • VTU / Anna / JNTU format reports
  • 20–25 slide PPT + 50+ viva Q&A
  • FPGA-ready synthesizable code
  • Mentoring via WhatsApp / Zoom
⚙️

RTL Design

Combinational, sequential, FSM, datapath

📡

Protocols

UART, SPI, I2C, AXI4-Lite

🧠

CPU & DSP

ALU, multipliers, FIR, simple cores

✅

Verification

Testbenches, assertions, coverage

Tools Used (RTL Flow Only)

Xilinx Vivado for synthesis/implementation · Siemens QuestaSim for simulation.

🔷Xilinx Vivado 📗Siemens QuestaSim 📜Verilog 📘SystemVerilog 🧩FPGA Flow 📈Waveform / Coverage

65+ Latest MTech VLSI Design RTL Project Topics (2026)

All topics are RTL-based and use Xilinx Vivado + Siemens QuestaSim. Languages: Verilog / SystemVerilog.

# Project Title Domain Tools
⚙️  Combinational RTL Design
1Parameterised N-bit Adder / Subtractor with Carry Look-AheadCombinationalVivado · QuestaSim · Verilog
2Priority Encoder and Decoder with Configurable WidthEncoder/DecoderVivado · QuestaSim · Verilog
3Barrel Shifter and Rotator RTL DesignShifterVivado · QuestaSim · Verilog
4Comparator and Equality Checker with Hierarchical DesignComparatorVivado · QuestaSim · Verilog
5Multiplexer / Demultiplexer Tree and Crossbar SwitchMux/CrossbarVivado · QuestaSim · Verilog
6BCD to 7-Segment and Binary to Gray Code ConvertersCode ConvertVivado · QuestaSim · Verilog
⏱️  Sequential RTL Design
7Synchronous and Asynchronous Counter Designs (Up/Down/Loadable)CountersVivado · QuestaSim · Verilog
8Shift Registers – SIPO, PISO, Universal Shift RegisterShift RegVivado · QuestaSim · Verilog
9Sequence Detector (Mealy and Moore) for Arbitrary PatternsSeq DetectorVivado · QuestaSim · Verilog
10Edge Detectors, Synchronisers and Clock Domain Crossing (CDC) FlopsCDCVivado · QuestaSim · SystemVerilog
11LFSR (Linear Feedback Shift Register) for PRBS GenerationLFSRVivado · QuestaSim · Verilog
12Debounce Circuit and Digital Filter for Mechanical SwitchesDebounceVivado · QuestaSim · Verilog
🔀  FSM Design
13Traffic Light Controller FSM with Pedestrian RequestTraffic FSMVivado · QuestaSim · Verilog
14Vending Machine Controller FSMVendingVivado · QuestaSim · Verilog
15Elevator Controller FSM for Multi-Floor SystemElevatorVivado · QuestaSim · Verilog
16UART Transmitter / Receiver FSM DesignUART FSMVivado · QuestaSim · Verilog
17SPI Master / Slave Protocol Engine FSMSPI FSMVivado · QuestaSim · Verilog
18I2C Master Controller FSM with Clock StretchingI2C FSMVivado · QuestaSim · Verilog
19Memory Controller FSM for SRAM / DRAM InterfaceMem Ctrl FSMVivado · QuestaSim · Verilog
20CRC Generator / Checker FSMCRCVivado · QuestaSim · Verilog
➕  Arithmetic Units
21Parameterised ALU with Arithmetic and Logic OperationsALUVivado · QuestaSim · Verilog
22Array Multiplier and Booth Multiplier RTL DesignMultiplierVivado · QuestaSim · Verilog
23Restoring and Non-Restoring DividerDividerVivado · QuestaSim · Verilog
24Fixed-Point Arithmetic Unit (Add, Mul, MAC)Fixed-PointVivado · QuestaSim · Verilog
25Floating-Point Adder (IEEE 754 Single Precision) – RTLFP AdderVivado · QuestaSim · SystemVerilog
26Square Root and CORDIC-based Trigonometric UnitCORDICVivado · QuestaSim · Verilog
27Pipeline Multiplier and Pipelined ALUPipelineVivado · QuestaSim · Verilog
📡  Communication Protocols (RTL)
28Full UART with Baud Rate Generator, TX and RXUARTVivado · QuestaSim · Verilog
29SPI Master with Configurable Clock Polarity and PhaseSPIVivado · QuestaSim · Verilog
30I2C Master with Multi-Byte Transfer and ACK HandlingI2CVivado · QuestaSim · Verilog
31AXI4-Lite Slave Interface for Register AccessAXI4-LiteVivado · QuestaSim · SystemVerilog
32AXI4 Stream Interface for Data Path BlocksAXI-StreamVivado · QuestaSim · SystemVerilog
33Simple Wishbone or Avalon-MM Compatible SlaveWishboneVivado · QuestaSim · Verilog
34PS/2 Keyboard or Mouse Interface ControllerPS/2Vivado · QuestaSim · Verilog
35VGA Controller for Text and Simple Graphics OutputVGAVivado · QuestaSim · Verilog
📶  DSP Blocks (RTL)
36FIR Filter – Direct Form and Transposed Form RTLFIRVivado · QuestaSim · Verilog
37IIR Filter – Biquad Cascade ImplementationIIRVivado · QuestaSim · Verilog
38Moving Average and CIC Filter for DecimationCIC / MAVivado · QuestaSim · Verilog
39FFT Butterfly Unit and Small Radix-2 FFT CoreFFTVivado · QuestaSim · Verilog
40Digital Mixer / NCO (Numerically Controlled Oscillator)NCOVivado · QuestaSim · Verilog
41PID Controller in Fixed-Point RTLPIDVivado · QuestaSim · Verilog
💾  Memory & Data Path
42Synchronous FIFO with Empty / Full Flags and Almost FlagsFIFOVivado · QuestaSim · Verilog
43Asynchronous FIFO for Clock Domain CrossingAsync FIFOVivado · QuestaSim · SystemVerilog
44Dual-Port RAM and Single-Port RAM Behavioural ModelsRAMVivado · QuestaSim · Verilog
45Stack (LIFO) and Queue Implementation in RTLStack/QueueVivado · QuestaSim · Verilog
46Simple Cache Controller (Direct-Mapped) RTLCacheVivado · QuestaSim · SystemVerilog
47DMA Controller for Memory-to-Memory TransferDMAVivado · QuestaSim · Verilog
🧠  CPU / Processor Cores (RTL)
488-bit / 16-bit Soft CPU with Instruction Set and DatapathSoft CPUVivado · QuestaSim · Verilog
49RISC-V RV32I Subset – Fetch, Decode, Execute PipelineRISC-VVivado · QuestaSim · SystemVerilog
50Single-Cycle vs Multi-Cycle Processor ComparisonCPU ArchVivado · QuestaSim · Verilog
51Pipelined Processor with Hazard Detection and ForwardingPipeline CPUVivado · QuestaSim · SystemVerilog
52Interrupt Controller and Exception Handling UnitInterruptVivado · QuestaSim · Verilog
53Simple SoC – CPU + UART + Timer + GPIO on AXI-LiteMini SoCVivado · QuestaSim · SystemVerilog
✅  Verification (QuestaSim Focused)
54Self-Checking Testbench for ALU / Multiplier with ScoreboardTestbenchQuestaSim · SystemVerilog
55Constrained Random Verification for Protocol ControllersCRVQuestaSim · SystemVerilog
56SystemVerilog Assertions (SVA) for FIFO and Handshake ProtocolsSVAQuestaSim · SystemVerilog
57Functional Coverage and Covergroups for Protocol VerificationCoverageQuestaSim · SystemVerilog
58UVM-Lite Testbench for AXI4-Lite SlaveUVM-LiteQuestaSim · SystemVerilog · UVM
59Bus Functional Model (BFM) for UART / SPIBFMQuestaSim · SystemVerilog
🚀  Advanced & FPGA-Oriented RTL
60Clock Gating and Low-Power RTL TechniquesLow PowerVivado · QuestaSim · Verilog
61Parameterised IP Core with AXI4-Lite Configuration RegistersIP CoreVivado · QuestaSim · SystemVerilog
62Hardware CRC32 / Checksum AcceleratorCRC AccelVivado · QuestaSim · Verilog
63Image Line Buffer and Simple Edge Detection RTL BlockImage RTLVivado · QuestaSim · Verilog
64AES Encryption Round Unit (RTL) – Educational SubsetCryptoVivado · QuestaSim · SystemVerilog
65End-to-End Mini SoC: CPU + Peripherals + AXI + QuestaSim Testbench + Vivado ImplementationFull SoCVivado · QuestaSim · SystemVerilog

★ All 65 MTech VLSI Design project topics are RTL-only and use Xilinx Vivado (synthesis, implementation) and Siemens QuestaSim (functional simulation, coverage). Languages: Verilog and SystemVerilog. Each package includes IEEE base paper, complete RTL source, testbenches, Vivado project files, QuestaSim scripts, university-format report for VTU / Anna University / JNTU, PPT (20–25 slides) and 50+ viva Q&A.

FAQ — MTech VLSI Design (RTL) Projects

Top topics include Parameterised ALU and multipliers, UART/SPI/I2C controllers, AXI4-Lite interconnect, FIR/IIR DSP filters, RISC-V style CPU core, FIFO and memory controllers, FSM-based protocol engines, and SystemVerilog testbenches with functional coverage in QuestaSim. All are pure RTL using Vivado and QuestaSim.
Xilinx Vivado for synthesis, implementation and bitstream generation. Siemens QuestaSim (or ModelSim) for functional simulation, waveform analysis and coverage. Languages: Verilog and SystemVerilog. Optional: VHDL for specific modules.
Yes. Every project includes IEEE style base paper, complete RTL source (Verilog/SystemVerilog), self-checking testbenches, Vivado project and constraint files, QuestaSim simulation scripts, university-format report (VTU, Anna University, JNTU), PPT (20–25 slides) and 50+ viva Q&A.
Typical completion is 7–18 working days. Simple combinational/sequential blocks: 7–10 days. Protocol controllers, DSP and CPU cores: 12–18 days. Contact +91 95919 12372 with your deadline.