PhD in Electronics & Communication Engineering

RTL-to-GDSII design of energy-efficient RISC-V cores with custom AI accelerators using Cadence Virtuoso, Synopsys Design Compiler and OpenROAD flow for near-threshold computing.

Design and evaluation of physical unclonable functions and true random number generators in advanced CMOS nodes with side-channel attack resilience analysis in Cadence and FPGA prototyping.

Thermal, signal-integrity and power-delivery modelling of multi-die chiplet systems using ANSYS HFSS/Icepak and Cadence Allegro — advanced packaging research aligned with industry roadmaps.

Analog/mixed-signal design of memristor-based and SRAM-based compute-in-memory arrays for energy-efficient DNN inference using Cadence Spectre and Synopsys Custom Compiler.

Model compression, quantisation and deployment of deep neural networks on STM32/ESP32/RISC-V microcontrollers with real-time inference and energy profiling for battery-powered IoT nodes.

Design of authenticated, encrypted OTA pipelines with remote attestation and rollback protection for resource-constrained IoT devices using ARM TrustZone and open-source RTOS.

Hardware/software co-design of multi-sensor fusion pipelines (IMU + camera + LiDAR) on Xilinx Zynq/Ultrascale+ platforms with Vivado HLS and PetaLinux for autonomous systems.

Ultra-low-power circuit design and protocol optimisation for batteryless IoT nodes powered by solar, RF or vibration energy — measured on custom PCB with USRP backhaul.

End-to-end system modelling of RIS-aided mmWave/THz links using NVIDIA Sionna, MATLAB and ray-tracing — joint beamforming and phase-shift optimisation with deep reinforcement learning.

Deep learning and generative models for high-mobility massive MIMO channel estimation and symbol detection under imperfect CSI — evaluated in Sionna and real USRP testbeds.

Waveform design and receiver algorithms that simultaneously support high-rate communication and high-resolution radar sensing for automotive and 6G applications using MATLAB and SDR platforms.

Channel modelling, Doppler compensation and multi-beam resource allocation for LEO satellite constellations serving direct-to-device and IoT traffic using Sionna and NS-3 extensions.

Full-wave EM design and optimisation of dual-polarised phased arrays and metasurface antennas at 28–140 GHz using ANSYS HFSS and CST Studio Suite with measured prototype validation.

System-level and circuit-level co-design of multi-band 5G/6G transceiver front-ends including PA linearisation, filter synthesis and EM co-simulation in ADS and Momentum.

Body-centric antenna design, SAR analysis and wireless power transfer modelling for medical implants and wearable sensors using HFSS, CST and tissue-equivalent phantoms.

Design of electronically reconfigurable metasurface antennas and reflectarrays for beam steering and multi-beam operation using full-wave simulation and varactor/PIN diode control circuits.

1D-CNN, Transformer and hybrid models for ECG arrhythmia detection, EEG seizure prediction and PPG-based vital-sign estimation with edge deployment on STM32/Jetson platforms.

Hardware implementation of CFAR detection, beamforming and point-cloud processing pipelines on Xilinx Ultrascale+ FPGAs using Vivado HLS and Vitis AI for autonomous vehicles.

Novel algorithms and hardware architectures for compressive sensing of sparse signals in spectrum sensing, medical imaging and array processing with FPGA and ASIC implementations.

U-Net variants with attention gates and transformer backbones for multi-modal MRI/CT segmentation, optimised for edge inference on NVIDIA Jetson and evaluated on public medical datasets.

Architecture exploration, quantisation-aware training and RTL implementation of domain-specific DNN accelerators with systolic arrays, sparsity support and power gating using Vivado and Cadence.

OFDM-based VLC transceiver design, LED non-linearity compensation and multi-user MIMO-VLC using MATLAB, experimental LED/photodiode prototypes and SDR platforms.

Design of approximate arithmetic units and quantum-inspired annealing circuits for energy-efficient AI and optimisation workloads with Cadence simulation and FPGA demonstration.

End-to-end open-source ASIC design (RTL → GDSII) using OpenROAD, OpenLane, SkyWater 130 nm PDK and Caravel harness — including tape-out readiness and post-silicon validation strategies.