PhD in Embedded Systems

Design and implementation of quantised CNN/Transformer accelerators on Xilinx Zynq Ultrascale+ using Vitis HLS, with power and latency profiling under PetaLinux for edge AI nodes.

Hardware/software co-design of IMU + camera + LiDAR fusion using Vivado IP Integrator, custom AXI peripherals and PetaLinux drivers for autonomous embedded platforms.

Dynamic partial reconfiguration of Xilinx FPGAs for runtime-adaptive DSP and ML workloads — floorplanning, bitstream management and seamless context switching on Zynq SoCs.

100 GbE packet parsing, classification and flow offload using Xilinx Versal ACAP and Vitis Networking libraries for software-defined networking and edge firewall applications.

End-to-end modelling of reconfigurable intelligent surface assisted mmWave/THz links using NVIDIA Sionna — joint beamforming, phase optimisation and deep reinforcement learning control.

Neural receivers and generative models for high-mobility massive MIMO channel estimation and detection under imperfect CSI, fully implemented and evaluated inside the Sionna research kit.

Waveform design and multi-objective optimisation for joint communication and radar sensing using Sionna’s differentiable link-level simulator for automotive and 6G scenarios.

Large-scale radio-map generation and site-specific channel modelling with Sionna RT, enabling digital-twin based network planning and AI training data generation for dense urban deployments.

System and circuit co-design of 28/39 GHz transceiver front-ends including PA linearisation, filter synthesis and EM co-simulation using Keysight PathWave ADS and Momentum.

Multi-channel phased-array feed network design, amplitude/phase calibration and mutual-coupling analysis using Keysight ADS for 5G/6G base-station and radar applications.

Automated synthesis and EM-verified layout of multi-band filters and impedance matching networks using ADS optimisation engines and Momentum for high-frequency embedded radios.

Behavioural modelling of power amplifiers, extraction of memory-polynomial coefficients and closed-loop digital predistortion evaluation entirely within the Keysight ADS environment.

Complete open-source ASIC implementation of a custom RISC-V or accelerator core using OpenROAD / OpenLane on SkyWater 130 nm or GlobalFoundries 180 nm, including timing closure and DRC clean GDSII.

Architecture exploration and physical design of energy-efficient open-source SoCs integrating domain-specific accelerators, fully implemented and verified through the OpenROAD autonomous flow.

Design, place-and-route and side-channel evaluation of PUF and TRNG blocks using OpenROAD on open PDKs, targeting secure embedded and IoT silicon.

Quantitative comparison of area, timing, power and turnaround time between OpenROAD and commercial tools on identical RTL benchmarks, contributing reproducible open-source methodology papers.