MTech VLSI Projects — IEEE 2026
50+ unique IEEE 2025–2026 MTech VLSI project topics in Bangalore. Full ASIC RTL-to-GDS flow, Cadence Virtuoso custom IC, Xilinx/Intel FPGA implementation, UVM functional verification and low-power CMOS design — with complete deliverables for VTU, Anna University, JNTU, Manipal and SRM MTech programmes.
Cadence Virtuoso
Synopsys DC / PT
Cadence Innovus
Xilinx Vivado / HLS
Intel Quartus Prime
Verilog / SystemVerilog
UVM Verification
ModelSim / QuestaSim
HSPICE / Spectre
Calibre DRC/LVS
MATLAB (DSP / ADC)
Python Verification
IEEE 2026 MTech VLSI Project Topics
Best unique IEEE 2025–2026 MTech VLSI topics covering ASIC, Verilog RTL, Cadence, FPGA, Low-Power, Mixed-Signal, Memory, UVM and Physical Design.
| # | Project Title (IEEE 2026) | Tools & Platform | Level |
|---|---|---|---|
| 1 | RISC-V 32-bit (RV32I) Processor Core ASIC Implementation — RTL, Synthesis, P&R and Timing Closure at 45 nm GPDK ASICIEEE 2026 | Verilog, Synopsys DC, Cadence Innovus, GPDK 45 nm | MTech |
| 2 | AES-256 Hardware Accelerator with Pipeline Architecture on Xilinx Zynq UltraScale+ — Area, Power and Throughput Analysis FPGAIEEE 2026 | SystemVerilog, Xilinx Vivado 2024, Zynq MPSoC | MTech |
| 3 | Low-Power 8T SRAM Cell with Read / Write Assist Circuits and Sense Amplifier at 45 nm FinFET-Equivalent GPDK MemoryIEEE 2026 | Cadence Virtuoso, HSPICE / Spectre, Calibre DRC/LVS | PhD |
| 4 | 10-bit 1-MSPS Successive Approximation Register (SAR) ADC Custom IC Layout in Cadence Virtuoso 180 nm — DRC/LVS/PEX Mixed-SignalIEEE 2026 | Cadence Virtuoso, Spectre, GPDK 180 nm, Calibre | PhD |
| 5 | Systolic Array Matrix Multiply Accelerator for DNN Inference — RTL to FPGA with Xilinx HLS and Vivado FPGA / HLSIEEE 2026 | Verilog / C++ HLS, Xilinx Vivado + Vitis HLS, Artix-7 | MTech |
| 6 | Approximate Wallace Tree Multiplier for Error-Tolerant Image Processing — ASIC Flow and Energy vs Accuracy Analysis ASICIEEE 2026 | Verilog, Synopsys DC, PrimeTime PX, GPDK 45 nm | MTech |
| 7 | UVM-Based Functional Verification of a PCIe 5.0 Transaction Layer with Scoreboard and Coverage-Driven Closure UVMIEEE 2026 | SystemVerilog, UVM 1.2, Synopsys VCS, DVE Waveform | MTech |
| 8 | Adaptive Body Biasing (ABB) for Sub-Threshold Leakage Reduction in IoT SoC at 28 nm CMOS Low PowerIEEE 2026 | Cadence Virtuoso, Spectre, HSPICE, GPDK 28 nm | PhD |
| 9 | Fault-Tolerant Carry-Select Adder with Triple Modular Redundancy (TMR) for Space-Grade FPGA — SEU Injection Test FPGAIEEE 2026 | VHDL, Xilinx Vivado, Kintex UltraScale, SEU Simulator | MTech |
| 10 | Second-Order Delta-Sigma ADC — Behavioural MATLAB → Verilog RTL → FPGA Prototyping on Nexys A7 Mixed-SignalIEEE 2026 | MATLAB, Verilog, Xilinx Vivado, Nexys A7 Artix-7 | MTech |
| 11 | Physical Design Flow for ARM Cortex-M0 Subsystem — Floorplan, CTS, Routing, IR Drop and EM Analysis at 45 nm Physical DesignIEEE 2026 | Cadence Innovus, Synopsys DC, Synopsys StarRC, GPDK 45 nm | PhD |
| 12 | Low-Power Ternary Content Addressable Memory (TCAM) Cell Array Design in 65 nm for Network Packet Classification MemoryIEEE 2026 | Cadence Virtuoso, HSPICE, Calibre DRC/LVS, GPDK 65 nm | PhD |
| 13 | High-Speed 64-bit Kogge-Stone Parallel Prefix Adder ASIC — RTL to GDS with Synopsys DC + Cadence Innovus ASICIEEE 2026 | Verilog, Synopsys DC / Genus, Cadence Innovus, GPDK 90 nm | MTech |
| 14 | Real-Time H.264 / AVC Video Encoder Hardware Accelerator on Xilinx Zynq SoC with AXI DMA Integration FPGA / SoCIEEE 2026 | Verilog / C, Xilinx Vivado + Vitis, Zynq-7000 SoC | PhD |
| 15 | Gate-Diffusion Input (GDI) Technique for Ultra-Low-Power Full Adder Cell in 45 nm — Power vs Delay Comparison Low PowerIEEE 2026 | Cadence Virtuoso, Spectre, GPDK 45 nm, PrimePower | MTech |
| 16 | LDPC Decoder Hardware Implementation for 5G NR — RTL Design and FPGA Verification on Xilinx Kintex-7 FPGA / 5GIEEE 2026 | SystemVerilog, Xilinx Vivado, Kintex-7 KC705, MATLAB BER | MTech |
| 17 | Two-Stage CMOS Op-Amp with Miller Compensation — Cadence Virtuoso Custom Layout, AC/Transient Simulation, DRC/LVS Analog ICIEEE 2026 | Cadence Virtuoso, Spectre, GPDK 180 nm, Calibre | MTech |
| 18 | FPGA Implementation of Turbo Encoder/Decoder for LTE using Max-Log-MAP Algorithm on Arria 10 FPGAIEEE 2026 | Verilog, Intel Quartus Prime, Arria 10 Dev Board, MATLAB | MTech |
| 19 | Power-Gating and Clock-Gating Co-Design for Leakage Reduction in ARM-Based SoC at 28 nm CMOS Low PowerIEEE 2026 | Verilog, Synopsys DC + PrimeTime PX, Cadence Innovus CPF | PhD |
| 20 | Neuromorphic Spike Neural Network (SNN) Accelerator ASIC — Leaky Integrate-and-Fire RTL and Synopsys DC Synthesis ASIC / AIIEEE 2026 | SystemVerilog, Synopsys DC, Cadence Innovus, GPDK 45 nm | PhD |
| 21 | Embedded DRAM (eDRAM) 6T Cell with Refresh Controller Design and Layout at 65 nm MemoryIEEE 2026 | Cadence Virtuoso, HSPICE, Calibre DRC/LVS, GPDK 65 nm | PhD |
| 22 | Formal Verification of AHB-Lite Bus Protocol Controller Using Cadence JasperGold Property Checking Formal VerificationIEEE 2026 | SystemVerilog Assertions (SVA), Cadence JasperGold, VCS | MTech |
| 23 | FinFET Inverter, NAND and NOR Standard Cell Design and Characterisation at 7 nm PDK with SPICE Netlist FinFET / 7 nmIEEE 2026 | Cadence Virtuoso, HSPICE / Spectre, 7 nm PTM/ASAP7 PDK | PhD |
| 24 | Noise-Shaping Flash ADC with Redundancy for High-Speed SERDES Receiver Front-End at 90 nm CMOS Mixed-SignalIEEE 2026 | Cadence Virtuoso, Spectre PSS/PAC, GPDK 90 nm, Calibre | PhD |
| 25 | Post-Quantum Cryptography — CRYSTALS-Kyber KEM Hardware Accelerator RTL and FPGA Verification FPGA / SecurityIEEE 2026 | Verilog, Xilinx Vivado, Zynq UltraScale+, PQC Test Vectors | PhD |
| 26 | Convolutional Neural Network (CNN) Inference ASIC — Dataflow Architecture, RTL and Power/Area Report at 28 nm ASIC / DNNIEEE 2026 | SystemVerilog, Synopsys DC, Cadence Innovus, GPDK 28 nm | PhD |
| 27 | Low-Dropout Regulator (LDO) with Fast Transient Response — Custom IC in Cadence Virtuoso 180 nm GPDK Analog ICIEEE 2026 | Cadence Virtuoso, Spectre, GPDK 180 nm, Calibre DRC/LVS | MTech |
| 28 | Advanced RISC Machine (ARM Cortex-M4) Soft Processor with FPU on Intel Cyclone V FPGA — RTOS Integration FPGA / SoCIEEE 2026 | Verilog, Intel Quartus, Cyclone V DE1-SoC, FreeRTOS | MTech |
* All MTech VLSI projects include IEEE 2026 base paper, Verilog/SystemVerilog RTL source, Cadence/Synopsys project files, simulation waveforms, DRC/LVS/PEX reports, FPGA bitstream, university-format report (VTU, Anna University, JNTU, Manipal), PPT and 40-question viva Q&A. WhatsApp to confirm topic availability and customisation.
MTech VLSI Project
— ASIC, Verilog RTL, Cadence, FPGA, Low-Power and Mixed-SignalWhat is an MTech VLSI Project?
An MTech VLSI project involves the design, simulation, synthesis, layout and verification of digital, analog or mixed-signal integrated circuits. It covers the complete RTL-to-GDS ASIC flow using industry-standard EDA tools — Cadence Virtuoso and Innovus, Synopsys Design Compiler, PrimeTime and Calibre — or FPGA prototyping using Xilinx Vivado or Intel Quartus. IEEE 2026 MTech VLSI projects address cutting-edge problems in AI hardware accelerators, 5G NR baseband, neuromorphic computing, post-quantum cryptography, FinFET memory and mixed-signal ADC/DAC design.
ASIC Design Flow for MTech VLSI Projects
The complete ASIC design flow used in our MTech VLSI projects in Bangalore: (1) RTL design and coding in Verilog/VHDL/SystemVerilog; (2) RTL simulation and functional verification using ModelSim, QuestaSim or VCS + UVM testbench; (3) Logic synthesis using Synopsys Design Compiler or Cadence Genus — area, timing and power report; (4) Static Timing Analysis (STA) with Synopsys PrimeTime; (5) Floorplanning, placement, Clock Tree Synthesis (CTS) and routing using Cadence Innovus; (6) Physical verification — DRC/LVS using Cadence Calibre; (7) Parasitic Extraction (PEX) and post-layout simulation; (8) GDSII tape-out submission.
FPGA Boards Used for MTech VLSI Projects
- Xilinx Basys 3 (Artix-7) — beginner / BE level
- Xilinx Nexys A7 (Artix-7) — BE / MTech level
- Xilinx Pynq-Z2 / ZedBoard (Zynq-7000 SoC)
- Xilinx ZCU102 (Zynq UltraScale+ MPSoC)
- Xilinx Kintex UltraScale KC705
- Intel Cyclone V DE1-SoC / DE10-Nano
- Intel Arria 10 GX FPGA Development Kit
- Xilinx Artix-7 KC160 Custom PCB
Cadence EDA Tools for MTech VLSI Projects
- Cadence Virtuoso — schematic, layout, DRC/LVS, PEX
- Cadence Spectre — SPICE, PSS, PAC, noise, transient
- Cadence Innovus — place-and-route, CTS, sign-off
- Cadence Genus — RTL synthesis, area/power optimisation
- Cadence JasperGold — formal verification, SVA property check
- Cadence Voltus — power integrity, IR drop, EM analysis
- Synopsys Design Compiler (DC) — logic synthesis, netlist
- Synopsys PrimeTime PX — STA and power signoff
- Synopsys VCS + DVE — RTL simulation, UVM coverage
- Synopsys StarRC — parasitic extraction
- Calibre DRC/LVS/PEX — Mentor Graphics physical verification
- GPDK 45 nm / 90 nm / 180 nm — process design kits
MTech VLSI Lab — Project Gallery
RISC-V ASIC RTL — Synopsys DC
SAR ADC — Cadence Virtuoso Layout
AES-256 FPGA — Xilinx Zynq
ARM SoC P&R — Cadence Innovus
PCIe UVM Verification — VCS
Frequently Asked Questions — MTech VLSI Projects
What are the best IEEE 2026 MTech VLSI project topics?
Best IEEE 2026 MTech VLSI topics include: RISC-V processor ASIC at 45 nm (Synopsys DC + Cadence Innovus); AES-256 pipeline accelerator on Zynq UltraScale+; 10-bit SAR ADC custom IC in Cadence 180 nm; systolic array DNN accelerator with Xilinx HLS; UVM-based PCIe 5.0 functional verification; 8T SRAM with read/write assist at 45 nm; adaptive body biasing for IoT SoC at 28 nm; LDPC decoder for 5G NR on Kintex-7; FinFET standard cell design at 7 nm; CNN inference ASIC at 28 nm; post-quantum CRYSTALS-Kyber FPGA accelerator — all with IEEE 2026 base paper, full RTL/Cadence source, synthesis reports, DRC/LVS, PPT and viva support.
What EDA tools are used for MTech VLSI projects in Bangalore?
Our MTech VLSI projects use: Cadence Virtuoso (schematic, custom layout, DRC/LVS, PEX), Cadence Innovus (P&R, CTS, timing closure), Cadence Spectre (SPICE/AMS/PSS/Pnoise), Cadence Genus (RTL synthesis), Cadence JasperGold (formal verification), Synopsys Design Compiler (logic synthesis), Synopsys PrimeTime PX (STA, power signoff), Synopsys VCS + UVM (functional verification), ModelSim/QuestaSim, Xilinx Vivado + Vitis HLS, Intel Quartus Prime, Calibre DRC/LVS and MATLAB for DSP/ADC behavioural modelling.
What deliverables are included in an MTech VLSI project?
Every MTech VLSI project from Projectsatbangalore includes: IEEE 2025–2026 base paper; complete Verilog/VHDL/SystemVerilog RTL source; Cadence Virtuoso schematic and DRC/LVS-clean layout (custom IC); synthesis netlist and area/power/timing report (Synopsys DC / Genus); P&R DEF and GDSII (Cadence Innovus); Calibre DRC/LVS verification log; FPGA bitstream and implementation reports (Vivado / Quartus); UVM testbench and coverage report; university-format project report (VTU, Anna University, JNTU, Manipal, SRM); PPT; working simulation demo video; and 40-question viva Q&A on CMOS, RTL, synthesis, timing, layout and EDA tools.
Can MTech VLSI projects be done on FPGA without Cadence or Synopsys licences?
Yes. FPGA-only MTech VLSI projects use Xilinx Vivado Webpack (free) or Intel Quartus Prime Lite (free) — no paid Cadence or Synopsys licence required. FPGA projects cover digital design, ASIC prototyping, processor soft-cores, hardware accelerators, DSP on FPGA, 5G NR baseband and security accelerators. For full ASIC flow (synthesis + P&R + DRC/LVS), we use campus-licenced EDA tool servers and deliver all netlist, layout and report files to the student.
Latest VLSI Projects for MTech
Get your IEEE 2026 MTech VLSI project with complete RTL source, Cadence/Synopsys files, FPGA implementation, DRC/LVS-clean layout, university-format report, PPT and full viva support — delivered on time for VTU, Anna University, JNTU and Manipal MTech submission. WhatsApp now for a free topic consultation.