V2G Power Flow Control — MATLAB Simulink
Bidirectional active and reactive power management from EV battery to utility grid using vector-controlled VSI, MOSFET/SiC gate driver hardware circuit, custom inductor and LCL filter design, and SOC-dependent dispatch — all modelled and simulated in MATLAB R2024b / Simulink / Simscape Electrical.
MATLAB R2024b
Simulink / Simscape
SimPowerSystems
LTspice (Gate Driver)
PSIM
PLECS
KiCad (Schematic)
Python (Post-processing)
V2G Bidirectional Power Flow Control — System Architecture
Active power dispatch · Reactive power support · Grid synchronisation · SOC limits · Protection logic
Flow Diagram 1 — V2G Power Flow Control Algorithm (Top-Level)
Grid Sensing
PLL / dq Transform
d-Axis (Active Power)
q-Axis (Reactive Power)
PWM & Gate Drive
DC-DC Converter
Grid Output
How the Power Flow Control Algorithm Works
The V2G power flow control algorithm operates in the synchronous reference frame (SRF) — a rotating dq coordinate system aligned with the grid voltage vector. This decouples active power (P) from reactive power (Q), allowing independent, precise control of each with simple PI regulators.
- Step 1 — Grid sensing: PT (potential transformer) and Hall-effect current transducers measure Vabc, Iabc at the PCC (point of common coupling).
- Step 2 — SRF-PLL: A software phase-locked loop extracts the grid phase angle θ and frequency f. The PLL bandwidth is 50 Hz to reject harmonic noise while tracking fundamental frequency accurately. In MATLAB, this is implemented using the Three-Phase PLL block (phaselock_threePhase) in Simscape Electrical.
- Step 3 — abc→dq transform: Clarke transform converts Vabc to Vαβ; Park transform using θ from the PLL converts to Vd, Vq. In a grid-aligned reference, Vd = |V| and Vq = 0, confirming synchronisation. The same transforms are applied to Iabc to get id and iq.
- Step 4 — Power calculation: P = 1.5·Vd·id and Q = −1.5·Vd·iq. P_ref comes from the SOC-based dispatch block; Q_ref is set for unity power factor (iq_ref = 0) or for voltage regulation.
- Step 5 — dq PI current control: Two PI controllers independently regulate id and iq. Cross-coupling terms (ωL·iq added to d-axis, −ωL·id added to q-axis) are feed-forwarded to improve dynamic response and eliminate steady-state error at 50 Hz.
- Step 6 — Inverse Park + SPWM: Vd_ref and Vq_ref are transformed back to three-phase Vabc_ref. A triangular carrier at fsw = 20 kHz generates 6 SPWM gate pulses for the three-phase VSI IGBT/SiC bridge.
MOSFET / SiC Gate Driver Circuit — Hardware Design
TLP250H optocoupler · Bootstrap high-side drive · Desaturation protection · Miller clamp · Deadtime
Circuit — MOSFET / SiC Gate Driver (Half-Bridge, Isolated Bootstrap)
DSP PWM Signals (3.3V)
Optocoupler Isolation
Gate Drive Output (+15/−5V)
Fault / DESAT Protection
SiC MOSFET (1200V)
Midpoint (to Inductor)
Isolated DC-DC Supply
MOSFET Gate Driver — Key Design Parameters
The gate driver is arguably the most critical component in a V2G bidirectional converter. A poor gate drive leads to excessive switching losses, EMI, and catastrophic failure from parasitic turn-on (shoot-through). The following specifications must be met for 20 kHz SiC operation at 700 V DC bus:
| Parameter | Value | Component / Reason |
|---|---|---|
| Gate drive IC | TLP250H | 2500 V isolation, 2.5 A peak gate current, 50 ns prop. delay |
| Turn-on gate voltage (Vgs+) | +15 V | Full channel inversion for SiC MOSFET (threshold 2–4 V) |
| Turn-off gate voltage (Vgs−) | −5 V | Negative bias prevents Miller-capacitance induced turn-on |
| Turn-on gate resistance (Rg_on) | 10 Ω | Slows dv/dt to < 20 V/ns, reduces EMI |
| Turn-off gate resistance (Rg_off) | 4.7 Ω | Faster turn-off reduces tail current loss |
| Bootstrap capacitor (Cboot) | 100 nF (X7R) | High-side supply charge reservoir, placed <5 mm from VCC pin |
| Deadtime | 200 ns | Set in DSP ePWM module; prevents shoot-through current |
| Desaturation threshold (Vce_sat) | 7 V | Fault tripping at 2× rated current; 1 µs blanking to ignore turn-on transient |
| Miller clamp | BSS316N (N-ch) | Rclamp = 2 Ω, prevents dv/dt induced gate voltage rise above threshold |
| Isolated gate supply | RECOM RPM5.0-1515S | +15/−5 V, 1.5 W, 1500 V isolation per half-bridge channel |
Bidirectional DC-DC Boost Inductor Design
Core selection · Air gap · Turns calculation · Copper loss · Saturation check · ETD49 ferrite
Circuit — Inductor Physical Construction and DC-DC Half-Bridge Context
Battery / LV Side
SiC MOSFET Half-Bridge
Boost Inductor (1 mH)
HV DC Bus (700V)
Midpoint Switching Node
ETD49 Core (N87)
Inductor Design Calculation — Step-by-Step
- Step 1 — Ripple current specification: Allowable inductor current ripple ΔiL = 20% of Irated = 0.20 × 60 A = 12 A peak-to-peak.
- Step 2 — Inductance required: From volt-seconds balance: L = Vin × D × (1−D) / (fsw × ΔiL) = 400 × 0.5 × 0.5 / (20 000 × 12) = 1.0 mH at duty cycle D = 0.5 (worst case).
- Step 3 — Peak current: Ipeak = IL_avg + ΔiL/2 = 60 + 6 = 66 A. Add 15% margin → 75 A peak for saturation check.
- Step 4 — Core selection: Choose ETD49 ferrite core (N87 material, µr = 2200). Effective area Ae = 2.11 cm², effective path le = 11.4 cm. Required AL = µ0 × µr × Ae / le without gap = 48 µH/turn² (before gap).
- Step 5 — Air gap: To achieve L = 1 mH with N turns, the gap dominates: lg = µ0 × Ae × N² / L. With N = 28 turns: lg = (4π×10⁻⁷ × 2.11×10⁻⁴ × 784) / 0.001 = 0.208 mm each leg × 2 sides (E-core has two gaps) ≈ 0.42 mm total (0.21 mm each gap face). Practical gap = 1.2 mm (accounting for fringing factor ~2).
- Step 6 — Flux density check: Bpeak = µ0 × N × Ipeak / lg = (4π×10⁻⁷ × 28 × 75) / 0.0012 = 2.2 T — this is wrong without fringing; with effective µe = 200: Bpeak = L × Ipeak / (N × Ae) = 0.001 × 75 / (28 × 2.11×10⁻⁴) = 0.127 T. Well below N87 Bsat = 420 mT at 100°C.
- Step 7 — Wire gauge: J = 4 A/mm² for natural cooling. Wire cross-section = 60/4 = 15 mm². Use 2 × AWG 8 (8.37 mm² each) Litz wire in parallel → 16.7 mm², 28 turns, DCR ≈ 4.8 mΩ, copper loss = 60² × 0.0048 = 17.3 W.
- Step 8 — Core loss: Using Steinmetz equation with N87 Kfe = 0.0044, α = 1.27, β = 2.4; Bac = ΔiL × L / (Ae × N × 2) = 0.027 T; Pcore ≈ 1.8 W at 20 kHz. Total loss = 17.3 + 1.8 = 19.1 W.
dq-Axis PI Current Control — Active and Reactive Power Regulation
SRF-PLL · Clarke / Park transform · Decoupled PI · Feed-forward · Cross-coupling compensation
dq Current Controller — PI Tuning by Internal Model Control (IMC)
The dq-axis current controller is tuned using the IMC (Internal Model Control) method, which gives a systematic relationship between bandwidth and PI gains. The plant model in the dq frame is a simple R-L circuit: G(s) = 1/(R + sL) where R = 0.1 Ω (filter resistance) and L = 1 mH (LCL filter converter-side inductor).
- Bandwidth selection: Current loop bandwidth ωc = 2π × 1000 rad/s (1 kHz, one decade below switching frequency 20 kHz). Allows 10 switching cycles per fundamental current period for adequate rejection.
- IMC PI gains: Kp = L × ωc = 0.001 × 6283 = 6.28 V/A. Ki = R × ωc = 0.1 × 6283 = 628.3 V·A⁻¹·s⁻¹. In MATLAB Discrete PID block: Kp = 2 (normalised), Ki = 150 (at Ts = 50 µs).
- Cross-coupling compensation: d-axis: Vd_ref = Vd_PI + ωL·iq_feedback. q-axis: Vq_ref = Vq_PI − ωL·id_feedback. This decouples the axes and eliminates steady-state error at 50 Hz.
- Anti-windup: Output saturation at ±Vdc/√3 (maximum modulation) with back-calculation anti-windup (Ka = 1/Kp) prevents integrator wind-up during current limiting.
- DC bus voltage outer loop: Bandwidth ωv = 2π × 50 rad/s (50 Hz, one decade below current loop). Kp_v = 0.2 A/V, Ki_v = 10 A·V⁻¹·s⁻¹. Generates id_ref ≤ Imax.
📄 V2G_PowerFlow_Init.m — System parameters and PI controller initialisation
MATLAB
%% V2G Power Flow Control — Initialisation Script % Projectsatbangalore.com | IEEE 2026 | V2G Power Flow Control MATLAB % Run before opening the Simulink model (.slx) %% — System parameters — clear; clc; Vbat = 400; % Battery nominal voltage [V] Vdc = 700; % DC bus voltage [V] Vgrid_L = 230; % Grid line-neutral rms [V] fgrid = 50; % Grid frequency [Hz] omega = 2*pi*fgrid; % Angular frequency [rad/s] Prated = 22000; % Rated V2G power [W] %% — LCL Filter — L1 = 1e-3; % Converter-side inductor [H] L2 = 0.5e-3; % Grid-side inductor [H] Cf = 10e-6; % Filter capacitor [F] Rd = 1.5; % Damping resistor [Ω] f_res = 1/(2*pi) * sqrt((L1+L2)/(L1*L2*Cf)); % Resonance freq. [Hz] fprintf('LCL resonance frequency: %.1f Hz\n', f_res); %% — Bidirectional DC-DC Inductor — Lb = 1e-3; % Boost inductor [H] Cin = 470e-6; % Input capacitor [F] Cdc = 1000e-6; % DC bus capacitor [F] fsw_dc = 20e3; % DC-DC switching frequency [Hz] D = (Vdc - Vbat) / Vdc; % Duty cycle ≈ 0.43 %% — SRF-PLL Parameters — Kp_pll = 100; % PLL proportional gain Ki_pll = 4000; % PLL integral gain Ts = 50e-6; % Simulation time step [s] (1/fsw) %% — dq Current Controller (IMC tuning) — wc_I = 2*pi*1000; % Current loop bandwidth [rad/s] Rfilter = 0.1; % Filter winding resistance [Ω] Kp_id = L1 * wc_I; % d-axis Kp = 6.28 V/A Ki_id = Rfilter * wc_I;% d-axis Ki = 628 V/A/s Kp_iq = Kp_id; % q-axis same (symmetric plant) Ki_iq = Ki_id; fprintf('d-axis PI: Kp=%.3f, Ki=%.1f\n', Kp_id, Ki_id); %% — DC Voltage Outer Loop — wc_V = 2*pi*50; % Voltage loop bandwidth [rad/s] Kp_vdc = Cdc * wc_V; % Voltage Kp = 0.314 A/V Ki_vdc = 10; % Voltage Ki [A/V/s] Imax = Prated / (1.5 * Vgrid_L * sqrt(2)); % Max d-axis current %% — SOC Dispatch Table — SOC_V2G_min = 30; % Minimum SOC for V2G discharge [%] SOC_G2V_max = 90; % Maximum SOC for G2V charging [%] f_deadband = 0.2; % Frequency deadband [Hz] (±0.2 Hz) droop_R = 0.04; % Droop coefficient (4% per Hz deviation) %% — Power Reference (from droop + SOC) — % Pref = -(1/R_droop) * delta_f (Hz deviation from 50 Hz) % Positive = V2G injection; Negative = G2V charging disp('Parameters loaded. Open V2G_PowerFlow_Control.slx');
📄 V2G_THD_Analysis.m — Post-simulation THD and harmonic spectrum
MATLAB
%% V2G Power Flow Control — THD and Harmonic Analysis % Run after simulation: collects Iabc from 'To Workspace' block if ~exist('Iabc', 'var') error('Run simulation first — Iabc workspace variable not found.'); end t = Iabc.time; ia = Iabc.signals.values(:,1); Fs = 1/(t(2)-t(1)); % Sampling frequency t0 = 0.1; % Skip first 100 ms transient idx = t >= t0; ia_s = ia(idx); %% FFT N = length(ia_s); Y = fft(ia_s) / N; f = (0:N/2) * Fs / N; amp = 2*abs(Y(1:N/2+1)); amp(1) = amp(1)/2; % DC component %% THD Calculation fund_idx = round(50 * N/Fs) + 1; I1 = amp(fund_idx); % Fundamental (50 Hz) harm_idx = round((100:50:5000) * N/Fs) + 1; harm_idx = harm_idx(harm_idx <= length(amp)); THD = 100 * sqrt(sum(amp(harm_idx).^2)) / I1; fprintf('Grid Current THD: %.2f%% (IEEE 519-2022 limit: 5%%)\n', THD); %% Plot spectrum figure; stem(f(1:200), amp(1:200), 'filled', 'Color', [0.85 0.47 0.04]); title(sprintf('V2G Grid Current Harmonic Spectrum — THD = %.2f%%', THD)); xlabel('Frequency (Hz)'); ylabel('Amplitude (A)'); xlim([0 5000]); grid on;
LCL Filter Design — Grid-Side Harmonic Attenuation
Converter inductor L1 · Filter capacitor Cf · Grid inductor L2 · Passive damping · Resonance
LCL Filter Design Equations and Procedure
The LCL filter provides superior high-frequency attenuation (−60 dB/decade above resonance) compared to an L-filter (−20 dB/decade), allowing a smaller and lighter magnetic component while meeting IEEE 519-2022 THD < 5% for grid-connected EV chargers.
| Component | Value | Design Equation / Constraint |
|---|---|---|
| L1 (converter-side) | 1.0 mH | ΔiL ≤ 20% Irated → L1 ≥ Vdc·D(1−D)/(fsw·ΔiL) = 0.875 mH, rounded to 1 mH |
| Cf (filter capacitor) | 10 µF | Reactive power ≤ 5% rated: Cf ≤ 0.05·Irated/(ωgrid·Vphase) = 13.8 µF; choose 10 µF X2 MKP |
| L2 (grid-side) | 0.5 mH | Ratio r = L2/L1 = 0.5; L2 ≥ L1/(2·r_max+1) = L1/5; choose 0.5 mH |
| Rd (passive damping) | 1.5 Ω | Rd = 1/(3·ωres·Cf) = 1/(3×9600π×10µF) = 1.1 Ω, choose 1.5 Ω |
| Resonance frequency | 3.86 kHz | fres = (1/2π)·√[(L1+L2)/(L1·L2·Cf)] must be: 10·fg < fres < fsw/2 |
| Attenuation at fsw | −62 dB | |H(jωsw)| = 1/|1−(ωsw/ωres)²| · 1/(L1+L2)Cf·ωsw²; harmonic current ratio i2/i1 < 0.3% |
| Total inductance Ltot | 1.5 mH | L1 + L2; defines voltage drop across filter: ΔV = ω·Ltot·Irated = 47.1 V (9% of 500 V) |
SOC-Based Power Dispatch — V2G Mode Logic
Droop frequency control · State machine · SOC guard · Pref computation · Stateflow / embedded MATLAB
Power Dispatch Algorithm — State Transitions
The SOC-based V2G/G2V mode selector runs as a Stateflow chart in Simulink, evaluated every 10 ms. It reads the grid frequency deviation Δf, current SOC, and grid voltage amplitude. The power reference Pref is computed from a frequency droop characteristic with SOC-weighted derating.
- State 1 — IDLE: |Δf| < 0.2 Hz. No power exchange. Maintains DC bus at 700 V. Transitions to V2G if Δf < −0.2 Hz and SOC > 30%, or to G2V if Δf > +0.2 Hz and SOC < 90%.
- State 2 — V2G DISCHARGE: Grid under-frequency (f < 49.8 Hz) detected. Pref = (−1/Rdroop) × Δf × SOC_factor, where SOC_factor = (SOC − 30%)/(90% − 30%). At SOC = 60%, SOC_factor = 0.5, so Pref = 50% of Pmax = 11 kW. Exit if SOC < 25% (emergency reserve) or Δf > 0.1 Hz.
- State 3 — G2V CHARGE: Grid over-frequency (f > 50.2 Hz) or off-peak tariff signal received. Pref = (1/Rdroop) × Δf × (1 − SOC_factor). Exit if SOC > 88% or Δf < −0.1 Hz.
- State 4 — FAULT: MOSFET overcurrent, DC bus overvoltage (>750 V), battery overtemperature (>45°C) or grid voltage sag (<0.85 pu). Disables all gate pulses, closes contactors. Latched until manual reset via CAN message.
- Droop coefficient: Rdroop = 0.04 (4% droop). At Δf = −0.5 Hz, Pref = 0.5/0.04 = 12.5 kW > Pmax — so Pref is clamped to Pmax = 22 kW. The SOC derating prevents deep discharge below the 20% buffer for EV driving range.
Simulink Output Waveforms — What You Will See
Grid current · DC bus voltage · Inductor current · Active/reactive power · SOC · Frequency response
Grid Current Ia (A)
Three-phase sinusoidal grid current after LCL filter. Fundamental at 50 Hz, THD < 3%, amplitude 63.7 A peak (22 kW at 230 V). Reverses polarity cleanly during G2V→V2G transition within 2 cycles.
DC Bus Voltage Vdc (V)
Regulated to 700 V with <1% steady-state ripple (7 V). Transient dip of <30 V (4%) during mode switch from IDLE to full V2G, recovering within 40 ms. Overshoot <5% during step load change.
Inductor Current iL (A)
Triangular ripple at 20 kHz superimposed on 60 A DC component. ΔiL = 12 A pp as designed. Current waveform reverses average during G2V charging mode — verified in Simulink Scope with cursors.
Active Power P (kW)
Calculated from P = 1.5·Vd·id in dq frame. Steps from 0 to +22 kW (V2G) in 40 ms, to −22 kW (G2V) in 45 ms. Steady-state error <0.5% at all operating points. Matches Pref from SOC dispatch.
Battery SOC (%)
Ramps from 80% to 30% over 1-hour V2G discharge at 22 kW (simulated in Simulink with 100× speed-up scaling). Coulomb-counting SOC matches actual Simscape Battery block SOC within ±0.5%.
MOSFET Gate Signals
Six SPWM gate pulses (S1–S6) at 20 kHz. 200 ns dead-time visible between complementary switch pairs. Gate voltage swings between +15 V and −5 V as designed. No shoot-through observed in DESAT monitor signal.
How to Build This Project in MATLAB Simulink
01
Set Up System Model
Create a new Simulink model. Add Simscape Electrical toolbox blocks: Battery (lithium-ion), Universal Bridge (IGBT/SiC), Three-Phase Source (11 kV, 50 Hz), Powergui (discrete, Ts = 50 µs). Set solver to Fixed-Step Discrete.
02
Build DC-DC Stage
Implement the bidirectional half-bridge: two IGBT blocks, boost inductor (1 mH), input capacitor (470 µF), DC bus capacitor (1000 µF). Add DC bus voltage measurement and PWM Generator block.
03
Implement PLL & dq Control
Use the Three-Phase PLL block (Simscape) to extract θ. Build Clarke and Park transform blocks using embedded MATLAB function blocks. Add two Discrete PI Controller blocks for id and iq with cross-coupling feed-forward. Connect Inverse Park transform to SPWM.
04
Add SOC Dispatch & Run
Build the Stateflow mode selector (V2G / G2V / IDLE / FAULT). Connect SOC signal from Simscape Battery block output. Verify mode transitions with step change in grid frequency. Run script V2G_PowerFlow_Init.m first, then simulate for 0.5 s. Use THD script to verify <3% grid current harmonic distortion.
Related Topics — V2G Power Flow Control MATLAB
V2G power flow control MATLAB
bidirectional power flow EV Simulink
MOSFET gate driver V2G circuit
SiC MOSFET bidirectional converter
inductor design DC-DC converter
ETD49 ferrite core inductor V2G
dq axis current control MATLAB
SRF-PLL Simulink three-phase
PI current controller dq frame
LCL filter design EV charger
SOC based V2G dispatch algorithm
droop frequency control EV grid
V2G reactive power compensation
SPWM 20 kHz VSI MATLAB
TLP250H gate driver optocoupler
bootstrap high-side gate drive
desaturation protection MOSFET
Miller clamp SiC gate driver
V2G IEEE 1547 grid standard
IEC 61851 EV charging standard
THD analysis V2G grid current
vehicle-to-grid Simulink project
EV battery bidirectional charger
V2G MATLAB project Bangalore
Projectsatbangalore — Complete V2G Power Flow Control Package (IEEE 2026): Full Simulink model (.slx) with dq-axis control, MOSFET gate driver schematic (KiCad), inductor design calculations, LCL filter design sheet, MATLAB initialisation scripts, THD analysis script, SOC dispatch Stateflow, IEEE 2026 base paper, annotated waveform results, university-format report (VTU / Anna University / NIT / IIT), PPT slides and viva Q&A coaching for EEE, ECE and EV-stream BE/BTech/MTech students. WhatsApp: +91 95919 12372
FAQ — V2G Power Flow Control MATLAB
How does dq-axis control decouple active and reactive power in V2G?
In the synchronous rotating frame (dq), the grid voltage vector is aligned to the d-axis so that Vq = 0. Under this condition P = 1.5·Vd·id and Q = −1.5·Vd·iq. Since Vd is constant (controlled by the grid), P depends only on id and Q only on iq. Two independent PI controllers regulate id and iq separately — by changing id_ref, active power is controlled precisely without affecting reactive power, and vice versa. Cross-coupling terms ±ωL·id/iq are added as feed-forward to eliminate the coupling inherent in the R-L plant at 50 Hz.
Why use SiC MOSFET instead of IGBT in a V2G converter?
SiC (Silicon Carbide) MOSFETs have three key advantages over Si IGBTs for V2G at 700 V DC bus: (1) No minority carrier storage — switching is 5–10× faster (td_on ≈ 18 ns vs 200 ns for IGBT), enabling 20 kHz operation with manageable switching loss; (2) Lower Rds(on) at high temperature — SiC maintains low on-resistance above 150°C unlike IGBT which degrades; (3) Zero reverse recovery — the body diode has negligible Qrr, drastically reducing freewheeling losses in the bidirectional topology. The result is a 2–3% efficiency improvement at 22 kW that directly translates to more energy delivered per V2G cycle.
What is shoot-through and how is it prevented in the V2G gate driver?
Shoot-through occurs when both Q_H and Q_L in a half-bridge are simultaneously ON, creating a short circuit across the 700 V DC bus and destroying both devices instantaneously. Prevention has three layers in this design: (1) Deadtime — the DSP ePWM module inserts a 200 ns blank period where both gate signals are LOW before turning on either switch; this guarantees the outgoing device has fully turned off before the incoming device turns on. (2) Negative gate bias — turning off with Vgs = −5 V prevents Miller capacitance (induced by the opposing switch's fast dv/dt) from raising the gate above threshold and causing spurious turn-on. (3) Miller clamp — a low-impedance N-channel MOSFET (BSS316N) actively holds the gate of the OFF device at −5 V during the switching transition of its partner.
How is the PLL implemented in MATLAB Simulink for V2G grid synchronisation?
The SRF-PLL (Synchronous Reference Frame PLL) is the standard approach for three-phase grid synchronisation in V2G. Implementation in Simulink: (1) Apply Clarke transform to Vabc to get Vα, Vβ; (2) Apply Park transform using the estimated angle θ̂ to get Vd, Vq; (3) Vq is the phase error signal — in steady state Vq = 0 when θ̂ = θgrid; (4) A PI controller drives Vq to zero and outputs ωe (estimated angular frequency); (5) Integrating ωe gives θ̂. The PI gains Kp_pll = 100, Ki_pll = 4000 give a PLL bandwidth of about 50 Hz. Under Simscape Electrical, the Three-Phase PLL (Discrete SRF PLL) block implements all of this; set Ts = 50 µs and Initial frequency = 50 Hz. The output angle θ is used in all Park/Inverse Park transforms in the current controller.
Can I get a complete V2G power flow control MATLAB project with MOSFET circuit and report in Bangalore?
Yes — Projectsatbangalore provides the complete package: full Simulink model (.slx) with dq-axis PI controller, SOC Stateflow, and LCL filter; KiCad gate driver schematic (TLP250H, bootstrap, DESAT, Miller clamp); inductor design calculation spreadsheet (ETD49, air gap, turns, copper/core loss); MATLAB scripts for initialisation and THD analysis; IEEE 2026 base paper; annotated waveform screenshots; university-format project report (VTU, Anna University, NIT, IIT); PPT slides; and viva Q&A coaching on power electronics, control theory, SiC devices, grid standards (IEEE 1547, IEC 61851, SAE J3068). WhatsApp +91 95919 12372 for pricing and topic list.