Tools & Platforms — Systolic Array FIR Filter Projects
Both FPGA implementation and simulation-only tracks are available — using the industry-standard toolchain for digital filter design, RTL implementation, functional verification and ASIC synthesis.
Xilinx Vivado 2024.2
Intel Quartus Prime
Verilog / System Verilog
VHDL
MATLAB DSP Toolbox
Simulink HDL Coder
ModelSim / QuestaSim
Cadence Genus / Innovus
Python / NumPy / SciPy
Xilinx Vitis HLS
MATLAB Fixed-Point Designer
Intel HLS Compiler
Systolic FIR Filter — Journal Publication Targets 2026
Mapping your systolic array FIR filter research to the right IEEE / Scopus journal based on architecture novelty, implementation platform and application domain.
IEEE TVLSI / TCAS-I
Top VLSI & Circuits Journals
Highest impact for FPGA/ASIC systolic FIR — IIT, NIT, IIITs
IEEE TVLSIIF 3.0 · Scopus Q2
IEEE TCAS-IIF 5.2 · Scopus Q1
IEEE TCAS-IIIF 4.0 · Scopus Q1
Avg. Review3–6 months
Best For
- FPGA systolic FIR with novel low-power / area technique
- ASIC systolic array with Cadence tape-out quality results
- QRD systolic beamforming array for radar/5G
- New multiplier-less / approximate computing FIR architecture
IEEE Access / TAES
Fast-Track & Application Journals
4–8 week review · SCI-E · VTU, Anna Univ., JNTU accepted
IEEE AccessIF 3.9 · SCI-E Q2
IEEE TAESIF 4.4 · Q1 (Radar FIR)
ETRI JournalScopus Q2 (5G FIR)
Review Time4–10 weeks
Best For
- 5G / SDR polyphase FIR filter FPGA implementation
- Radar pulse-compression systolic FIR on Zynq
- Adaptive LMS systolic FIR for ECG / biomedical
- Reconfigurable FIR filter for SDR / cognitive radio
What We Deliver
Complete Project Package
All deliverables — no hidden charges
RTL CodeVerilog / VHDL (clean)
SimulationFunctional + Timing TB
FPGA ReportUtilisation + Timing
MATLAB RefFloating ↔ Fixed-Point
Includes
- Vivado / Quartus project files (.xpr / .qpf)
- Testbench with MATLAB golden reference comparison
- SNR, ENOB, power & resource comparison table
- IEEE-format manuscript + LaTeX + PPT + Viva Q&A
Systolic FIR Filter Architecture Domains
12 architecture categories covering every known systolic and pipelined FIR filter topology used in 2026 VLSI, FPGA and DSP research.
1D Linear Systolic Array
N-tap PE chain, full-throughput, every PE computes one MAC per clock
2D Systolic Array FIR
2D PE mesh for 2D convolution / image filter on Zynq / UltraScale+
Distributed Arithmetic
LUT-based multiplier-free FIR — serial DA, parallel DA, offset-binary DA
CORDIC FIR
Rotation-based multiply-less FIR using CORDIC algorithm iterations
Polyphase FIR
Efficient multi-rate filtering — interpolation, decimation, SRC for 5G NR
Adaptive FIR (LMS / RLS)
Systolic LMS, delayed LMS, block LMS, RLS systolic for noise cancellation
QRD Systolic Array
QR decomposition systolic for beamforming, MIMO equalisation, RLS
Low-Power / Approximate
Clock gating, operand isolation, approximate multiplier, GALS FIR
Image / Video FIR
2D Gaussian, Sobel, Laplacian, bilateral filter on Zynq HLS
5G / Radar FIR
Root-raised cosine, matched filter, pulse compression systolic FIR
Reconfigurable FIR
Run-time coefficient update, DA-LUT reload, multi-standard SDR FIR
ASIC / Semi-Custom
Cadence Genus RTL synthesis, Innovus P&R, DRC/LVS systolic FIR macro
FPGA-Based Systolic Array FIR Filter Projects
RTL-level Verilog / VHDL implementation on Xilinx Artix-7, Kintex-7, Zynq-7000, UltraScale+ or Intel Cyclone V / Arria 10 — synthesised, placed & routed in Vivado or Quartus with full resource utilisation, timing closure and power estimation reports.
| # | Project Title | Architecture | Platform | Journal |
|---|---|---|---|---|
| 01 | 16-Tap 1D Systolic Array FIR Filter in Verilog on Artix-7 — DSP48E2 Inference, 500 MHz Timing Closure | Systolic | Vivado / Artix-7 | IEEE TVLSI |
| 02 | 32-Tap Pipelined Transposed FIR Filter on Zynq-7000 — Post-Layout Power vs Direct-Form Comparison | Transposed | Vivado / Zynq | IEEE Access |
| 03 | 64-Tap Distributed Arithmetic FIR (Fully-Parallel) on Kintex-7 — LUT vs DSP Power-Area Trade-Off | DA-FIR | Vivado / Kintex-7 | IEEE TCAS-II |
| 04 | Folded Systolic Array FIR — Hardware Sharing with Retiming for 8× Area Reduction on Artix-7 | Folded | Vivado | IEEE TVLSI |
| 05 | Semi-Systolic Farrow FIR Filter for Fractional Delay — Fixed-Point Vivado Implementation at 300 MHz | Farrow | Vivado / Kintex | IEEE TCAS-I |
| 06 | 2D Systolic FIR for 1080p Real-Time Gaussian Blur on Zynq UltraScale+ with AXI-Stream Interface | 2D Systolic | Vivado / ZU+ | IEEE Access |
| 07 | Reconfigurable Systolic FIR Filter with Run-Time Coefficient Reload via AXI Lite on Artix-7 | Reconfig | Vivado | IEEE TCAS-II |
| 08 | Polyphase Decimation FIR (1:8) for 5G NR Channel Filtering on Kintex UltraScale — 100 MSPS | Polyphase | Vivado / KU | IEEE TAES |
| 09 | Root-Raised Cosine (RRC) Matched FIR Filter for 5G NR — Systolic FPGA at 200 MHz, EVM < 1% | RRC / 5G | Vivado | IEEE Access |
| 10 | CORDIC-Based 32-Tap FIR on FPGA — Multiplier-Free Implementation with SNR > 60 dB | CORDIC | Vivado / Artix | IEEE TCAS-II |
| 11 | LMS Adaptive Systolic FIR for ECG Noise Cancellation on Zynq — Real-Time Coefficient Update at 10 kHz | LMS | Vivado / Zynq | IEEE TCAS-I |
| 12 | Block LMS Systolic Array FIR for Acoustic Noise Cancellation — 64-Channel FPGA at 48 kHz | Block LMS | Vivado / KU | IEEE Access |
| 13 | QRD Systolic Array for 4×4 MIMO Beamforming FIR — FPGA Implementation with Givens Rotations | QRD | Vivado / UltraScale | IEEE TCAS-I |
| 14 | Carry-Save Adder (CSA) Systolic FIR — Reducing Critical Path by 35% vs Ripple-Carry on Artix-7 | CSA | Vivado | IEEE TVLSI |
| 15 | Low-Power DA-FIR with Clock Gating on Cyclone V — 40% Dynamic Power vs Xilinx DSP Reference | Low Power | Quartus / Cyclone V | IEEE TCAS-II |
| 16 | High-Level Synthesis (HLS) Systolic FIR — Vitis HLS Directives for DSP Mapping on Kintex-7 | HLS | Vitis HLS / Vivado | IEEE Access |
| 17 | TDM-Multiplexed Systolic FIR for 8-Channel ECG Processing — Single FPGA, 8× Channel Sharing | TDM-MUX | Vivado / Artix | IEEE TCAS-II |
| 18 | Pulse Compression Matched FIR Filter for Radar on Zynq UltraScale+ — 1 GHz Clocking, 256-Tap | Radar | Vivado / ZU+ | IEEE TAES |
| 19 | Approximate Multiplier-Based Systolic FIR for IoT Edge — 50% Power vs Exact IEEE 754 Reference | Approx. | Vivado / Artix | IEEE TVLSI |
| 20 | FPGA Floating-Point Systolic FIR Using DSP48E2 Cascade — 32-bit IEEE 754 Single Precision | Float | Vivado / Kintex | IEEE Access |
| 21 | Systolic FIR Filter for Software-Defined Radio (SDR) on Intel Arria 10 — 100 MHz IF Sampling | SDR | Quartus / Arria 10 | IEEE TAES |
| 22 | Wavelet-Based Systolic FIR Filterbank for EEG Signal Processing on Zynq — 8-Band Decomposition | Wavelet | Vivado / Zynq | IEEE TCAS-I |
| 23 | Systolic Sparse FIR Filter — Coefficient Pruning for 60% LUT Saving on Artix-7 | Sparse | Vivado | IEEE TVLSI |
| 24 | GALS (Globally Asynchronous Locally Synchronous) Systolic FIR — Multi-Clock Domain FPGA Design | GALS | Vivado / UltraScale | IEEE TCAS-I |
| 25 | Parameterised Systolic FIR IP Core in SystemVerilog — Generic N-Tap with AXI4-Stream Wrapper | IP Core | Vivado IP Packager | IEEE Access |
Simulation-Based Systolic Array FIR Filter Projects
MATLAB / Simulink algorithmic modelling, Simulink HDL Coder RTL export, Cadence Genus / Innovus ASIC synthesis, Python / SciPy filter design and fixed-point behavioural verification — no physical FPGA board required.
| # | Project Title | Architecture | Tool | Journal |
|---|---|---|---|---|
| 01 | MATLAB Systolic Array FIR Simulation — Floating-Point vs 16-bit Fixed-Point SNR Comparison (32-Tap) | Simulation | MATLAB / Fixed-Point | IEEE TCAS-II |
| 02 | Simulink HDL Coder Systolic FIR — Model-Based Design to RTL Flow with Code Coverage Verification | Simulink | Simulink HDL Coder | IEEE Access |
| 03 | Cadence Genus ASIC Synthesis of 64-Tap Systolic FIR — 28nm GPDK, Timing, Power, Area Reports | ASIC | Cadence Genus / 28nm | IEEE TVLSI |
| 04 | Cadence Innovus Place & Route of Systolic FIR Macro — DRC/LVS Clean, Physical GDS-II Output | P&R | Cadence Innovus | IEEE TVLSI |
| 05 | Python SciPy Systolic FIR Design — Parks-McClellan Equiripple, Kaiser, Remez Algorithm Comparison | Python | Python / NumPy | IEEE Access |
| 06 | MATLAB DA-FIR Simulation — LUT Content Generation, Serial vs Parallel Computation SNR vs Speed | DA-FIR | MATLAB | IEEE TCAS-II |
| 07 | ModelSim RTL Simulation of 128-Tap Pipelined FIR — Waveform Analysis vs MATLAB Golden Reference | RTL Sim | ModelSim | IEEE Access |
| 08 | MATLAB LMS Adaptive Systolic FIR Simulation — Convergence Rate, Misadjustment vs Step Size Study | LMS Sim | MATLAB | IEEE TCAS-I |
| 09 | Simulink Polyphase FIR Filterbank Simulation — 5G NR SCS 15 kHz / 30 kHz Prototype Filter Design | Polyphase | Simulink | IEEE Access |
| 10 | Cadence Virtuoso + Spectre Transistor-Level Systolic FIR Cell — 45nm CMOS Power vs Speed Simulation | Transistor | Cadence Spectre | IEEE TCAS-I |
| 11 | MATLAB 2D Systolic FIR Convolution Engine — Image Noise Reduction SNR vs Kernel Size Trade-Off | 2D Conv | MATLAB Image Proc. | IEEE Access |
| 12 | Monte-Carlo Fixed-Point Simulation — Word-Length Optimisation for Systolic FIR Coefficient Quantisation | Fixed-Point | MATLAB Fixed-Point | IEEE TCAS-II |
| 13 | QRD Systolic Array MATLAB Simulation — Givens Rotation vs Gram-Schmidt Stability for Beamforming | QRD | MATLAB | IEEE TCAS-I |
| 14 | Approximate Computing DA-FIR MATLAB Simulation — Mean Error Distance vs Bit-Width for IoT DSP | Approx. | MATLAB | IEEE TVLSI |
| 15 | Farrow Structure FIR MATLAB Simulation — Variable Fractional Delay for Radar Pulse Compression | Farrow | MATLAB | IEEE TAES |
Distributed Arithmetic (DA) & CORDIC FIR Projects
| # | Project Title | Type | Platform | Journal |
|---|---|---|---|---|
| 01 | Fully-Parallel DA FIR Filter — B-bit LUT Precomputation, Carry-Save Addition Tree on Artix-7 | DA | Verilog / Vivado | IEEE TCAS-II |
| 02 | Serial DA-FIR for Low-Area Audio Processing — 1-bit-per-cycle Accumulation, 20-bit Resolution | Serial DA | VHDL / Vivado | IEEE Access |
| 03 | Offset-Binary DA FIR — Eliminating Sign-Extension Overhead, 12% LUT Reduction vs Standard DA | OB-DA | Vivado | IEEE TCAS-II |
| 04 | Decomposed DA FIR — ROM Splitting for 256-Tap Filter on Kintex-7, Distributed BRAM Usage | Decomposed | Vivado / Kintex | IEEE TVLSI |
| 05 | CORDIC Vectoring Mode Systolic FIR — Rotation-Based Coefficient Multiplication for Hearing Aid DSP | CORDIC | Verilog / Artix | IEEE TCAS-I |
| 06 | Double-CORDIC Systolic FIR — Simultaneous Sine/Cosine Multiplication for Complex Bandpass FIR | D-CORDIC | Vivado | IEEE TCAS-II |
Polyphase, Multi-Rate & Adaptive Systolic FIR Projects
| # | Project Title | Type | Platform | Journal |
|---|---|---|---|---|
| 01 | Polyphase Interpolation FIR (×4) for 5G FR1 Baseband Upsampling — 307.2 MHz Output on Kintex | Interp. | Vivado / Kintex | IEEE Access |
| 02 | CIC + Polyphase Compensation FIR Filter for SDR — 125 MHz Passband, 60 dB Stop-Band Attenuation | CIC-Comp | Vivado | IEEE TAES |
| 03 | Delayed LMS Systolic FIR — Removing Critical-Path Multiplier Feedback for High-Speed FPGA | D-LMS | Vivado / Artix | IEEE TCAS-I |
| 04 | Normalised LMS (NLMS) Systolic FIR Filter — FPGA Implementation for Acoustic Echo Cancellation | NLMS | Vivado / Zynq | IEEE Access |
| 05 | RLS Systolic Array FIR — Fast Convergence Channel Equaliser for OFDM Receiver on Kintex-7 | RLS | Vivado / Kintex | IEEE TCAS-I |
| 06 | Variable Bandwidth FIR via Polyphase Decomposition — FPGA SRC for Multi-Standard Radio | V-BW | Vivado | IEEE Access |
Application-Domain Systolic FIR Projects — 5G, Radar, Image, ECG
| # | Project Title | Domain | Platform | Journal |
|---|---|---|---|---|
| 01 | 5G NR Prototype Filter (FBMC/OFDM) Systolic FIR on UltraScale — 1024-Tap, 491.52 MHz CPRI Rate | 5G NR | Vivado / UltraScale | IEEE Access |
| 02 | FMCW Radar Pulse Compression Matched FIR — 256-Tap Systolic on Zynq MPSoC for 77 GHz ADAS | Radar | Vivado / ZU+ | IEEE TAES |
| 03 | Anti-Jam GPS Receiver Adaptive Systolic FIR Beamformer — 8-Element Array LMS on Kintex UltraScale | GPS/Radar | Vivado / KU | IEEE TAES |
| 04 | Real-Time 4K UHD Sobel Edge Detection 2D Systolic FIR on Zynq — 60 fps, AXI-Stream, HLS IP | 4K Video | Vitis HLS / Zynq | IEEE Access |
| 05 | Medical Ultrasound Beamforming Systolic FIR Array on Artix-7 — 128-Channel Delay-and-Sum Filter | Ultrasound | Vivado / Artix | IEEE TCAS-I |
| 06 | 12-Lead ECG Baseline Wander Removal Systolic FIR on Zynq — 0.05 Hz HP Filter at 500 Hz Sampling | ECG | Vivado / Zynq | IEEE Access |
| 07 | Hearing Aid Fractional Delay FIR Farrow on ARM-FPGA — Sub-sample Delay Compensation for WOLA | Hearing Aid | Vivado / Zynq | IEEE TCAS-II |
| 08 | Deep-Learning-Aided Systolic FIR Coefficient Optimisation — RL-Based Bit-Width Allocation on FPGA | AI-FIR | Vivado + Python RL | IEEE TVLSI |
Low-Power, Reconfigurable & ASIC Systolic FIR Projects
| # | Project Title | Type | Tool | Journal |
|---|---|---|---|---|
| 01 | Low-Power Systolic FIR with Dynamic Voltage-Frequency Scaling (DVFS) on Cadence — 28nm GPDK | DVFS | Cadence Genus | IEEE TVLSI |
| 02 | ASIC Systolic FIR with Canonical Signed Digit (CSD) Multiplier — 45% Adder Count Reduction | CSD | Cadence Genus / 45nm | IEEE TVLSI |
| 03 | Sub-Expression Sharing (SES) Systolic FIR — Common Sub-Expression Elimination for Multi-Constant | SES | Cadence / MATLAB | IEEE TCAS-II |
| 04 | Low-Voltage (0.7V) Systolic FIR in FINFET 16nm — Near-Threshold Timing Analysis with Cadence Tempus | NTV | Cadence Tempus | IEEE TCAS-I |
| 05 | Runtime-Reconfigurable Systolic FIR — Partial Reconfiguration on Kintex UltraScale, <2ms Swap | PR-FPGA | Vivado PR / KU | IEEE TCAS-I |
| 06 | Multi-Standard Systolic FIR — Switching Between LTE/5G/Wi-Fi Prototype Filter in Single Vivado Design | Multi-Std | Vivado | IEEE Access |
| 07 | AI-Optimised VLSI FIR Layout — Reinforcement Learning for Macro Placement of Systolic Array in Innovus | AI-VLSI | Cadence Innovus + RL | IEEE TVLSI |
All 60+ topics include RTL code (Verilog/VHDL) or MATLAB/Simulink model, testbench, simulation waveforms, FPGA resource/timing/power reports or ASIC synthesis results, MATLAB golden-reference comparison, IEEE-format manuscript (LaTeX/Word), university-format report and 30-question viva Q&A. Contact us for the full topic list with base paper abstracts.
Systolic FIR Project Delivery — 4 Stages
01
Architecture Selection & Spec
We confirm the FIR filter specification (tap count, precision, throughput, target board), select the optimal systolic architecture (DA, CORDIC, polyphase, LMS, QRD) and validate novelty against 2023–2026 IEEE Xplore papers.
02
MATLAB / Python Design & Reference
Floating-point filter design using Parks-McClellan / Kaiser window, coefficient quantisation study (SNR vs word-length), fixed-point behavioural model in MATLAB Fixed-Point Designer or Python, frequency response plots and passband/stopband verification.
03
RTL / ASIC Implementation & Simulation
Verilog / VHDL RTL coding of systolic PE array, testbench with stimulus from MATLAB golden reference, functional simulation in ModelSim/QuestaSim, synthesis in Vivado/Quartus or Cadence Genus, timing closure and power estimation — all reports included.
04
Manuscript & Publication
IEEE-format double-column LaTeX manuscript with block diagram, architecture table, resource comparison vs prior art, SNR/power/area results and conclusion — submitted to IEEE TVLSI, TCAS-I, TCAS-II, TAES or IEEE Access with reviewer response support.
What Students Say
★★★★★
"My 32-tap DA-FIR project on Artix-7 was published in IEEE TCAS-II. The team delivered full Vivado project, testbench, MATLAB reference and LaTeX manuscript — everything I needed for my VTU MTech submission."
MTech VLSI, VTU · DA-FIR Artix-7 · IEEE TCAS-II 2025
★★★★★
"I needed a MATLAB simulation project for my PhD — they designed a QRD systolic array with Givens rotation and published it in IEEE TCAS-I. Exceptional understanding of systolic array theory."
PhD ECE, Anna University · QRD Systolic · IEEE TCAS-I 2025
★★★★★
"Reconfigurable polyphase FIR for 5G NR on Kintex UltraScale — implemented in Verilog with full AXI-Stream wrapper and published in IEEE Access within 6 weeks. Best FPGA project support in Bangalore."
MTech DSP, NIT · Polyphase FIR · IEEE Access 2026
Frequently Asked Questions
What are the best systolic array FIR filter project topics for MTech and PhD in 2026?
Best IEEE 2026 systolic array FIR filter topics include: Low-Power 16-tap DA-FIR on Artix-7, CORDIC-Based Pipelined FIR for 5G NR, 2D Systolic Array FIR for Real-Time Image Convolution on Zynq, Reconfigurable FIR using DA-LUT for SDR, Folded Systolic FIR with Retiming, Polyphase FIR for 5G SRC, QRD Systolic Array for Adaptive Beamforming, Semi-Systolic Farrow FIR for Radar, TDM Multiplexed Systolic FIR for ECG, and AI-Optimised VLSI FIR Layout. All implemented in Verilog/VHDL on Vivado or MATLAB/Cadence with IEEE publication support.
What is a systolic array FIR filter and how does it differ from direct-form FIR?
A systolic array FIR replaces the single MAC chain of direct-form FIR with a 1D/2D array of identical Processing Elements (PEs) computing partial MACs and passing results rhythmically to adjacent cells. Advantages: (1) High throughput — one output per clock cycle; (2) Regular VLSI layout — identical PEs simplify routing; (3) Scalable — add taps by adding PE cells. On FPGA, each PE maps to one DSP48 slice, enabling 256-tap systolic FIR at 500+ MHz on UltraScale+.
What is Distributed Arithmetic (DA) FIR and why is it popular for FPGA?
DA-FIR replaces hardware multipliers with a precomputed LUT indexed by input data bits, accumulating results serially bit-by-bit. Since FPGAs have abundant LUT resources, DA-FIR achieves higher throughput at lower power than DSP-multiplier FIR on the same device. Ideal for 64–512 tap filters in SDR, radar, ECG and hearing-aid DSP where multiplier-free area efficiency is critical.
Which IEEE journals publish systolic array FIR filter research?
Top IEEE journals: IEEE Transactions on VLSI Systems (IF 3.0, Q2 — ASIC/FPGA FIR architecture), IEEE Transactions on Circuits and Systems I (IF 5.2, Q1 — adaptive/QRD systolic FIR), IEEE TCAS-II (IF 4.0 — compact brief format, faster review), IEEE Transactions on Aerospace and Electronic Systems (IF 4.4 — radar/5G systolic FIR), and IEEE Access (IF 3.9, SCI-E — fast 4–8 week review, good for deadline-constrained PhD students).
Can I do a simulation-only systolic FIR project without an FPGA board?
Yes. Simulation-only tracks include: MATLAB algorithmic model with fixed-point analysis, Simulink HDL Coder RTL generation and simulation, Cadence Genus ASIC synthesis (28nm/45nm GPDK) with area/power/timing reports, Cadence Innovus place-and-route with DRC/LVS, ModelSim RTL functional simulation, and Python/SciPy coefficient design with SNR analysis. All are accepted for IEEE TVLSI, TCAS-II and IEEE Access publications — no physical FPGA required.
Systolic Array FIR Filter Projects — Bangalore & Across India
Systolic FIR Projects — Bangalore
Vivado · Quartus · Cadence · Verilog · VHDL · MATLAB · IEEE TVLSI
- FPGA and ASIC systolic FIR projects for VTU, MSRIT, BMS, RVCE, Amrita PhD/MTech scholars
- Xilinx Vivado 2024.2 and Intel Quartus Prime projects with timing closure reports
- Cadence Genus + Innovus ASIC synthesis and P&R for PhD VLSI scholars
- IEEE TVLSI, TCAS-I, TCAS-II and IEEE Access manuscript preparation and submission
- MATLAB floating-point to fixed-point analysis and SNR trade-off study
- Same-day consultation for MTech project selection and novelty check
VTUMSRITBMSRVCEAmritaRNSIT
Systolic FIR Projects — Pan India (Online)
Chennai · Hyderabad · Pune · Cochin · Delhi · Remote Delivery
- Anna University, JNTU, NIT, CUSAT, SPPU Pune systolic FIR project support online
- Full online delivery via Google Drive — RTL files, Vivado project, MATLAB code, reports
- IEEE Access fast-track submission for tight PhD/MTech deadlines — 4–8 week review
- MATLAB simulation-only track for scholars without FPGA board access
- Emergency 72-hour FPGA synthesis and testbench for deadline-critical MTech students
- Mock viva with 30 systolic FIR / FPGA / DSP Q&A answers customised to your project
Anna Univ.JNTUNITCUSATSPPUOsmania